External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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11.2. Timing Report DDR

The Report DDR task in the Timing Analyzer generates custom timing margin reports for all EMIF IP instances in your design. The Timing Analyzer generates this custom report by sourcing the wizard-generated <variation_name>_report_timing.tcl script.

This <variation_name>_report_timing.tcl script reports the following timing slacks on specific paths of the DDR SDRAM:

  • Read capture
  • Read resynchronization
  • Mimic, address and command
  • Core
  • Core reset and removal
  • Half-rate address and command
  • DQS versus CK
  • Write
  • Write leveling (tDQSS)
  • Write leveling (tDSS/tDSH)
  • DQS Gating (Postamble)

The <variation_name>_report_timing.tcl script checks basic design rules and assumptions; if violations are found, you receive critical warnings when the Timing Analyzer runs during compilation or when you run the Report DDR task.

To generate a timing margin report, follow these steps:

  1. Compile your design in the Intel® Quartus® Prime software.
  2. Launch the Timing Analyzer.
  3. Double-click Report DDR from the Tasks pane. This action automatically executes the Create Timing Netlist, Read SDC File, and Update Timing Netlist tasks for your project.
  • The .sdc may not be applied correctly if the variation top-level file is the top-level file of the project. You must have the top-level file of the project instantiate the variation top-level file.

The Report DDR feature creates a new DDR folder in the Timing Analyzer Report pane.

Expanding the DDR folder reveals the detailed timing information for each PHY timing path, in addition to an overall timing margin summary for the instance, as shown in the following figure.

Figure 93. Timing Margin Summary Window Generated by Report DDR Task

Timing Margin Summary Window Generated by Report DDR Task

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