External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 3/11/2022
Public

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13.7.3. On-Chip Debug Port for Intel® Stratix® 10 EMIF IP

The EMIF On-Chip Debug Port allows user logic to access the same calibration data used by the EMIF Toolkit, and allows user logic to send commands to the sequencer. You can use the EMIF On-Chip Debug Port to access calibration data for your design and to send commands to the sequencer just as the EMIF Toolkit would. The following information is available:
  • Pass/fail status for each DQS group
  • Read and write data valid windows for each group

In addition, user logic can request the following commands from the sequencer:

  • Destructive recalibration of all groups
  • Masking of groups and ranks
  • Generation of per-DQ pin margining data as part of calibration

The user logic communicates through an Avalon® -MM slave interface as shown below.

Figure 156. User Logic Access


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