Intel® Quartus® Prime Pro Edition User Guide: Third-party Simulation

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ID 683870
Date 10/05/2021
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Intel FPGA Simulation Basics 3. Questa*-Intel® FPGA Edition, ModelSim* , and Questa* Simulator Support 4. Synopsys VCS* and VCS MX Support 5. Aldec Active-HDL and Riviera-PRO Support 6. Cadence Xcelium* Parallel Simulator Support 7. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive A. Intel® Quartus® Prime Pro Edition User Guides
2. Intel FPGA Simulation Basics x
What's New in this Version? 2.1. Supported Simulators 2.2. Supported Simulation Levels 2.3. Supported Hardware Description Languages 2.4. Supported Simulation Flows 2.5. Preparing for Simulation 2.6. Running a Simulation (Custom Flow) 2.7. Intel FPGA Simulation Basics Revision History
2.5. Preparing for Simulation x
2.5.1. Compiling Simulation Model Libraries 2.5.2. Using The EDA Netlist Writer 2.5.3. Simulating Intel® FPGA IP Cores
2.5.3. Simulating Intel® FPGA IP Cores x
2.5.3.1. Generating IP Simulation Files 2.5.3.2. Scripting IP Simulation
2.5.3.2. Scripting IP Simulation x
2.5.3.2.1. Generating a Combined Simulator Setup Script ( Intel® Quartus® Prime Pro Edition) 2.5.3.2.2. Incorporating Simulator Setup Scripts from the Generated Template
3. Questa*-Intel® FPGA Edition, ModelSim* , and Questa* Simulator Support x
3.1. Quick Start Example (ModelSim with Verilog) 3.2. Questa*-Intel® FPGA Edition, ModelSim, and Questa Simulator Guidelines 3.3. ModelSim Simulation Setup Script Example 3.4. Sourcing ModelSim* Simulator Setup Scripts 3.5. Unsupported Features 3.6. Questa*-Intel® FPGA Edition, ModelSim* , and Questa* Simulator Support Revision History
3.2. Questa*-Intel® FPGA Edition, ModelSim, and Questa Simulator Guidelines x
3.2.1. Using Questa*-Intel® FPGA Edition Precompiled Libraries 3.2.2. Passing Parameter Information from Verilog HDL to VHDL 3.2.3. Viewing Simulation Messages 3.2.4. Generating Signal Activity Data for Power Analysis 3.2.5. Viewing Simulation Waveforms 3.2.6. Simulating with Questa*-Intel® FPGA Edition Waveform Editor
3.2.4. Generating Signal Activity Data for Power Analysis x
3.2.4.1. Generating Standard Delay Output for Power Analysis
4. Synopsys VCS* and VCS MX Support x
4.1. Quick Start Example (VCS with Verilog) 4.2. VCS and VCS MX Guidelines 4.3. VCS Simulation Setup Script Example 4.4. Sourcing Synopsys VCS* MX Simulator Setup Scripts 4.5. Sourcing Synopsys VCS* Simulator Setup Scripts 4.6. Synopsys VCS* and VCS MX Support Revision History
5. Aldec Active-HDL and Riviera-PRO Support x
5.1. Quick Start Example (Active-HDL VHDL) 5.2. Aldec Active-HDL and Riviera-PRO Guidelines 5.3. Using Simulation Setup Scripts 5.4. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts 5.5. Aldec Active-HDL* and Riviera-PRO * Support Revision History
6. Cadence Xcelium* Parallel Simulator Support x
6.1. Using the Command-Line Interface 6.2. Sourcing Cadence Xcelium* Simulator Setup Scripts 6.3. Cadence Xcelium* Parallel Simulator Support Revision History
1. Answers to Top FAQs
2. Intel FPGA Simulation Basics
3. Questa*-Intel® FPGA Edition, ModelSim* , and Questa* Simulator Support
4. Synopsys VCS* and VCS MX Support
5. Aldec Active-HDL and Riviera-PRO Support
6. Cadence Xcelium* Parallel Simulator Support
7. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Intel® Quartus® Prime Pro Edition User Guides

2. Intel FPGA Simulation Basics

This document describes Intel® Quartus® Prime software support for simulating designs that target Intel FPGA devices. Simulation allows you to verify your design's behavior before configuring the FPGA device with the verified design. You specify input vectors to your simulator, and then the simulator determines and reports the expected corresponding outputs during the time period you specify.

Figure 1.  Questa*-Intel® FPGA Edition Wave Window

Prior to simulation, you compile the RTL or gate-level representation of your design and testbench. You must also compile IP simulation models, models from the Intel FPGA simulation libraries, and any other model libraries required for your design.

The Intel FPGA simulation process involves setting up your supported simulator working environment, compiling simulation model libraries, generating simulation files, running your simulator, and interpreting the results.

What's New in this Version?

  • The Intel® Quartus® Prime software adds new support for the Questa*-Intel® FPGA Edition simulator.
  • The Intel® Quartus® Prime software removes support for the ModelSim-Intel FPGA Edition simulator.
  • Intel® Quartus® Prime software supports updated third-party simulator versions and platforms.
  • The name of Mentor Graphics* is now Siemens* EDA.
  • For change details, refer to the Document Revision History.
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