University Self-Guided Lab: Introduction to Simulation and Debug of FPGAs (OUWSDBUG)

38 Minutes Online Course

Course Description

This online course consists of a 40 minute lecture and demonstrations and roughly two hours of self-guided laboratory exercises to learn the fundamentals of logic simulation and FPGA debugging tools available in the Quartus FPGA development tools using the Terasic DE10-Lite development kit. The laboratory exercises give the student hands on experience with ModelSim simulation, In-system Sources and Probes, and the Signal Tap in-chip logic analyzer. You will need to acquire the DE10-Lite development board from Terasic’s website or from electronic distributors such as Mouser or Digikey. The lab manual can be found in the resources section of this online class.

At Course Completion

You will be able to:

  • Understand the fundamental processes for Simulating a design and debugging
  • Use ModelSim to effectively simulate designs and identify faults in it
  • Use In-system Sources and Probes to probe at nodes in design and be able to observe hardware problem live
  • Use Signal Tap Logic Analyzer to be able to trigger events from clock edges and analyze those events as they happened in hardware

Skills Required

  • Basic understanding of Boolean combinational logic and sequential logic
  • Minimal experience in a software language such as C, Java, or Python

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

Applicable Training Curriculum

This course is part of the following Intel FPGA training curriculum:

Class Schedule

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