External Memory Interfaces Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683408
Date 3/29/2021
Public

1. Design Example Quick Start Guide for External Memory Interfaces Intel® Stratix® 10 FPGA IP

Updated for:
Intel® Quartus® Prime Design Suite 21.1
IP Version 19.2.3
A new interface and more automated design example flow is available for Intel® Stratix® 10 external memory interfaces.

The Example Designs tab in the parameter editor allows you to specify the creation of synthesis and simulation file sets which you can use to validate your EMIF IP.

You can generate an example design specifically for an Intel FPGA development kit, or for any EMIF IP that you generate.

Figure 1. General Design Example Workflows
Figure 2. Generating an EMIF Example Design With an Intel® Stratix® 10 Development Kit

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