External Memory Interfaces Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683408
Date 3/29/2021

2.2. Simulation Example Design

The simulation example design contains the major blocks shown in the following figure.
  • An instance of the synthesis example design. As described in the previous section, the synthesis example design contains a traffic generator and an instance of the memory interface. These blocks default to abstract simulation models where appropriate for rapid simulation.
  • A memory model, which acts as a generic model that adheres to the memory protocol specifications. Frequently, memory vendors provide simulation models for their specific memory components that you can download from their websites.
  • A status checker, which monitors the status signals from the external memory interface IP and the traffic generator, to signal an overall pass or fail condition.
Figure 9. Simulation Example Design

If you are using the Ping Pong PHY feature, the simulation example design includes two traffic generators issuing commands to two independent memory devices through two independent controllers and a common PHY, as shown in the following figure.

Figure 10. Simulation Example Design for Ping Pong PHY

If you are using RLDRAM 3, the traffic generator in the simulation example design communicates directly with the PHY using AFI, as shown in the following figure.

Figure 11. Simulation Example Design for RLDRAM 3 Interfaces

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