External Memory Interfaces Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683408
Date 3/29/2021
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Document Table of Contents
Document Table of Contents x
1. Design Example Quick Start Guide for External Memory Interfaces Intel® Stratix® 10 FPGA IP 2. Design Example Description for External Memory Interfaces Intel® Stratix® 10 FPGA IP 3. Document Revision History for External Memory Interfaces Intel® Stratix® 10 FPGA IP Design Example User Guide
1. Design Example Quick Start Guide for External Memory Interfaces Intel® Stratix® 10 FPGA IP x
1.1. Creating an EMIF Project 1.2. Generating and Configuring the EMIF IP 1.3. Generating the Synthesizable EMIF Design Example 1.4. Generating the EMIF Design Example for Simulation 1.5. Simulation Versus Hardware Implementation 1.6. Simulating External Memory Interface IP With ModelSim 1.7. Pin Placement for Intel® Stratix® 10 EMIF IP 1.8. Compiling and Programming the Intel® Stratix® 10 EMIF Design Example 1.9. Debugging the Intel® Stratix® 10 EMIF Design Example
1.2. Generating and Configuring the EMIF IP x
1.2.1. Intel® Stratix® 10 EMIF Parameter Editor Guidelines
2. Design Example Description for External Memory Interfaces Intel® Stratix® 10 FPGA IP x
2.1. Synthesis Example Design 2.2. Simulation Example Design 2.3. Example Designs Interface Tab
1. Design Example Quick Start Guide for External Memory Interfaces Intel® Stratix® 10 FPGA IP
2. Design Example Description for External Memory Interfaces Intel® Stratix® 10 FPGA IP
3. Document Revision History for External Memory Interfaces Intel® Stratix® 10 FPGA IP Design Example User Guide

1.2.1. Intel® Stratix® 10 EMIF Parameter Editor Guidelines

Table 1.  EMIF Parameter Editor Guidelines
Parameter Editor Tab Guidelines
General Ensure that the following parameters are entered correctly:
  • The speed grade for the device.
  • The memory clock frequency.
  • The PLL reference clock frequency.
Memory
  • Refer to the data sheet for your memory device to enter the parameters on the Memory tab.
  • You should also enter a specific location for the ALERT# pin. (Applies to DDR4 memory protocol only.)
Mem I/O
  • For initial project investigations, you may use the default settings on the Mem I/O tab.
  • For advanced design validation, you should perform board simulation to derive optimal termination settings.
FPGA I/O
  • For initial project investigations, you may use the default settings on the FPGA I/O tab.
  • For advanced design validation, you should perform board simulation with associated IBIS models to select appropriate I/O standards.
Mem Timing
  • For initial project investigations, you may use the default settings on the Mem Timing tab.
  • For advanced design validation, you should enter parameters according to your memory device's data sheet.
Board
  • For initial project investigations, you may use the default settings on the Board tab.
  • For advanced design validation and accurate timing closure, you should perform board simulation to derive accurate intersymbol interference (ISI)/crosstalk and board and package skew information, and enter it on the Board tab.
Controller Set the controller parameters according to the desired configuration and behavior for your memory controller.
Diagnostics You can use the parameters on the Diagnostics tab to assist in testing and debugging your memory interface.
Example Designs The Example Designs tab lets you generate design examples for synthesis and for simulation. The generated design example is a complete EMIF system consisting of the EMIF IP and a driver that generates random traffic to validate the memory interface.

For detailed information on individual parameters, refer to the appropriate chapter for your memory protocol in the Intel Stratix 10 External Memory Interfaces IP User Guide .

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