External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

2. Functional Description— Intel® Stratix® 10 EMIF IP

Intel® Stratix® 10 devices can interface with external memory devices clocking at frequencies of up to 1.3 GHz. The external memory interface IP component for Stratix 10 devices provides a single parameter editor for creating external memory interfaces, regardless of memory protocol. Unlike earlier EMIF solutions which used protocol-specific parameter editors to create memory interfaces via a complex RTL generation method, the Stratix® 10 EMIF solution captures the protocol-specific hardened EMIF logic of the Stratix 10 device together with more generic soft logic.

The Stratix® 10 EMIF solution is designed with the following implementations in mind:

Hard Memory Controller and Hard PHY

This implementation provides a complete external memory interface, based on the hard memory controller and hard PHY that are part of the Stratix® 10 silicon. An Avalon-MM interface is available for integration with user logic.

Soft Memory Controller and Hard PHY

This implementation provides a complete external memory interface, using an Intel-provided soft-logic-based memory controller and the hard PHY that is part of the Stratix® 10 silicon. An Avalon-MM interface is available for integration with user logic.

Custom Memory Controller and Hard PHY (PHY only)

This implementation provides access to the Altera PHY interface (AFI), to allow use of a custom or third-party memory controller with the hard PHY that is part of the Stratix® 10 silicon. Because only the PHY component is provided by Intel, this configuration is also known as PHY only.

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