External Memory Interface Handbook Volume 3: Reference Material

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ID 683841
Date 7/24/2019
Public
Document Table of Contents

7.4.3.1. Enabling the AXI Interface

This section provides guidance for enabling the AXI interface.

  1. To enable the AXI interface, first open in an editor the file appropriate for the required flow, as indicated below:
    • For synthesis flow: <working_dir>/<variation_name>/<variation_name>_c0.v
    • For simulation flow: <working_dir>/<variation_name>_sim/<variation_name>/<variation_name>_c0.v
    • Example design fileset for synthesis: <working_dir>/<variation_name>_example_design/example_project/<variation_name>_example/submodules/<variation_name>_example_if0_c0.v
    • Example design fileset for simulation: <working_dir>/<variation_name>_example_design/simulation/verilog/submodules/<variation_name>_example_sim_e0_if0_c0.v
  2. Locate and remove the alt_mem_ddrx_mm_st_converter instantiation from the .v file opened in the preceding step.
  3. Instantiate the alt_mem_ddrx_axi_st_converter module into the open .v file. Refer to the following code fragment as a guide:
    module ? # ( parameter
    // AXI parameters
    AXI_ID_WIDTH = <replace parameter value>,
    AXI_ADDR_WIDTH = <replace parameter value>,
    AXI_LEN_WIDTH = <replace parameter value>,
    AXI_SIZE_WIDTH = <replace parameter value>,
    AXI_BURST_WIDTH = <replace parameter value>,
    AXI_LOCK_WIDTH = <replace parameter value>,
    AXI_CACHE_WIDTH = <replace parameter value>,
    AXI_PROT_WIDTH = <replace parameter value>,
    AXI_DATA_WIDTH = <replace parameter value>,
    AXI_RESP_WIDTH = <replace parameter value>
    )
    (
    // Existing ports
    ...
    // AXI Interface ports
    // Write address channel
    input wire [AXI_ID_WIDTH - 1 : 0] awid,
    input wire [AXI_ADDR_WIDTH - 1 : 0] awaddr,
    input wire [AXI_LEN_WIDTH - 1 : 0] awlen,
    input wire [AXI_SIZE_WIDTH - 1 : 0] awsize,
    input wire [AXI_BURST_WIDTH - 1 : 0] awburst,
    input wire [AXI_LOCK_WIDTH - 1 : 0] awlock,
    input wire [AXI_CACHE_WIDTH - 1 : 0] awcache,
    input wire [AXI_PROT_WIDTH - 1 : 0] awprot,
    input wire awvalid,
    output wire awready,
    // Write data channel
    input wire [AXI_ID_WIDTH - 1 : 0] wid,
    input wire [AXI_DATA_WIDTH - 1 : 0] wdata,
    input wire [AXI_DATA_WIDTH / 8 - 1 : 0] wstrb,
    input wire wlast,
    input wire wvalid,
    output wire wready,
    // Write response channel
    output wire [AXI_ID_WIDTH - 1 : 0] bid,
    output wire [AXI_RESP_WIDTH - 1 : 0] bresp,
    output wire bvalid,
    input wire bready,
    // Read address channel
    input wire [AXI_ID_WIDTH - 1 : 0] arid,
    input wire [AXI_ADDR_WIDTH - 1 : 0] araddr,
    input wire [AXI_LEN_WIDTH - 1 : 0] arlen,
    input wire [AXI_SIZE_WIDTH - 1 : 0] arsize,
    input wire [AXI_BURST_WIDTH - 1 : 0] arburst,
    input wire [AXI_LOCK_WIDTH - 1 : 0] arlock,
    input wire [AXI_CACHE_WIDTH - 1 : 0] arcache,
    input wire [AXI_PROT_WIDTH - 1 : 0] arprot,
    input wire arvalid,
    output wire arready,
    // Read data channel
    output wire [AXI_ID_WIDTH - 1 : 0] rid,
    output wire [AXI_DATA_WIDTH - 1 : 0] rdata,
    output wire [AXI_RESP_WIDTH - 1 : 0] rresp,
    output wire rlast,
    output wire rvalid,
    input wire rready
    );
    // Existing wire, register declaration and instantiation
    ...
    // AXI interface instantiation
    alt_mem_ddrx_axi_st_converter #
    (
    .AXI_ID_WIDTH (AXI_ID_WIDTH ),
    .AXI_ADDR_WIDTH (AXI_ADDR_WIDTH ),
    .AXI_LEN_WIDTH (AXI_LEN_WIDTH ),
    .AXI_SIZE_WIDTH (AXI_SIZE_WIDTH ),
    .AXI_BURST_WIDTH (AXI_BURST_WIDTH ),
    .AXI_LOCK_WIDTH (AXI_LOCK_WIDTH ),
    .AXI_CACHE_WIDTH (AXI_CACHE_WIDTH ),
    .AXI_PROT_WIDTH (AXI_PROT_WIDTH ),
    .AXI_DATA_WIDTH (AXI_DATA_WIDTH ),
    .AXI_RESP_WIDTH (AXI_RESP_WIDTH ),
    .ST_ADDR_WIDTH (ST_ADDR_WIDTH ),
    .ST_SIZE_WIDTH (ST_SIZE_WIDTH ),
    .ST_ID_WIDTH (ST_ID_WIDTH ),
    .ST_DATA_WIDTH (ST_DATA_WIDTH ),
    .COMMAND_ARB_TYPE (COMMAND_ARB_TYPE)
    )
    a0
    (
    .ctl_clk (afi_clk),
    .ctl_reset_n (afi_reset_n),
    .awid (awid),
    .awaddr (awaddr),
    .awlen (awlen),
    .awsize (awsize),
    .awburst (awburst),
    .awlock (awlock),
    .awcache (awcache),
    .awprot (awprot),
    .awvalid (awvalid),
    .awready (awready),
    .wid (wid),
    .wdata (wdata),
    .wstrb (wstrb),
    .wlast (wlast),
    .wvalid (wvalid),
    .wready (wready),
    .bid (bid),
    .bresp (bresp),
    .bvalid (bvalid),
    .bready (bready),
    .arid (arid),
    .araddr (araddr),
    .arlen (arlen),
    .arsize (arsize),
    .arburst (arburst),
    .arlock (arlock),
    .arcache (arcache),
    .arprot (arprot),
    .arvalid (arvalid),
    .arready (arready),
    .rid (rid),
    .rdata (rdata),
    .rresp (rresp),
    .rlast (rlast),
    .rvalid (rvalid),
    .rready (rready),
    .itf_cmd_ready (ng0_native_st_itf_cmd_ready),
    .itf_cmd_valid (a0_native_st_itf_cmd_valid),
    .itf_cmd (a0_native_st_itf_cmd),
    .itf_cmd_address (a0_native_st_itf_cmd_address),
    .itf_cmd_burstlen (a0_native_st_itf_cmd_burstlen),
    .itf_cmd_id (a0_native_st_itf_cmd_id),
    .itf_cmd_priority (a0_native_st_itf_cmd_priority),
    .itf_cmd_autoprecharge (a0_native_st_itf_cmd_autopercharge),
    .itf_cmd_multicast (a0_native_st_itf_cmd_multicast),
    .itf_wr_data_ready (ng0_native_st_itf_wr_data_ready),
    .itf_wr_data_valid (a0_native_st_itf_wr_data_valid),
    .itf_wr_data (a0_native_st_itf_wr_data),
    .itf_wr_data_byte_en (a0_native_st_itf_wr_data_byte_en),
    .itf_wr_data_begin (a0_native_st_itf_wr_data_begin),
    .itf_wr_data_last (a0_native_st_itf_wr_data_last),
    .itf_wr_data_id (a0_native_st_itf_wr_data_id),
    .itf_rd_data_ready (a0_native_st_itf_rd_data_ready),
    .itf_rd_data_valid (ng0_native_st_itf_rd_data_valid),
    .itf_rd_data (ng0_native_st_itf_rd_data),
    .itf_rd_data_error (ng0_native_st_itf_rd_data_error),
    .itf_rd_data_begin (ng0_native_st_itf_rd_data_begin),
    .itf_rd_data_last (ng0_native_st_itf_rd_data_last),
    .itf_rd_data_id (ng0_native_st_itf_rd_data_id)
    );
  4. Set the required parameters for the AXI interface. The following table lists the available parameters.
  5. Export the AXI interface to the top-level wrapper, making it accessible to the AXI master.
  6. To add the AXI interface to the Quartus Prime project:
    • On the Assignments > Settings menu in the Quartus Prime software, open the File tab.
    • Add the alt_mem_ddrx_axi_st_converter.v file to the project.

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