Visible to Intel only — GUID: hco1416492594966
Ixiasoft
Visible to Intel only — GUID: hco1416492594966
Ixiasoft
5.5.5. Soft Controller Register Map
Address |
Bit |
Name |
Default |
Access |
Description |
---|---|---|---|---|---|
0x100 |
0 |
Reserved. |
0 |
— |
Reserved for future use. |
1 |
Reserved. |
0 |
— |
Reserved for future use. |
|
2 |
Reserved. |
0 |
— |
Reserved for future use. |
|
7:3 |
Reserved. |
0 |
— |
Reserved for future use. |
|
13:8 |
Reserved. |
0 |
— |
Reserved for future use. |
|
30:14 |
Reserved. |
0 |
— |
Reserved for future use. |
|
0x110 |
15:0 |
AUTO_PD_CYCLES |
0x0 |
Read write |
The number of idle clock cycles after which the controller should place the memory into power-down mode. The controller is considered to be idle if there are no commands in the command queue. Setting this register to 0 disables the auto power-down mode. The default value of this register depends on the values set during the generation of the design. |
16 |
Reserved. |
0 |
— |
Reserved for future use. |
|
17 |
Reserved. |
0 |
— |
Reserved for future use. |
|
18 |
Reserved. |
0 |
— |
Reserved for future use. |
|
19 |
Reserved. |
0 |
— |
Reserved for future use. |
|
21:20 |
ADDR_ORDER |
00 |
Read write |
00 - Chip, row, bank, column.01 - Chip, bank, row, column.10 - reserved for future use.11 - Reserved for future use. |
|
22 |
Reserved. |
0 |
— |
Reserved for future use. |
|
24:23 |
Reserved. |
0 |
— |
Reserved for future use. |
|
30:24 |
Reserved |
0 |
— |
Reserved for future use. |
|
0x120 |
7:0 |
Column address width |
— |
Read write |
The number of column address bits for the memory devices in your memory interface. The range of legal values is 7-12. |
15:8 |
Row address width |
— |
Read write |
The number of row address bits for the memory devices in your memory interface. The range of legal values is 12-16. |
|
19:16 |
Bank address width |
— |
Read write |
The number of bank address bits for the memory devices in your memory interface. The range of legal values is 2-3. |
|
23:20 |
Chip select address width |
— |
Read write |
The number of chip select address bits for the memory devices in your memory interface. The range of legal values is 0-2. If there is only one single chip select in the memory interface, set this bit to 0. |
|
31:24 |
Reserved. |
0 |
— |
Reserved for future use. |
|
0x121 |
31:0 |
Data width representation (word) |
— |
Read only |
The number of DQS bits in the memory interface. This bit can be used to derive the width of the memory interface by multiplying this value by the number of DQ pins per DQS pin (typically 8). |
0x122 |
7:0 |
Chip select representation |
— |
Read only |
The number of chip select in binary representation. For example, a design with 2 chip selects has the value of 00000011. |
31:8 |
Reserved. |
0 |
— |
Reserved for future use. |
|
0x123 |
3:0 |
tRCD |
— |
Read write |
The activate to read or write a timing parameter. The range of legal values is 2-11 cycles. |
7:4 |
tRRD |
— |
Read write |
The activate to activate a timing parameter. The range of legal values is 2-8 cycles. |
|
11:8 |
tRP |
— |
Read write |
The precharge to activate a timing parameter. The range of legal values is 2-11 cycles. |
|
15:12 |
tMRD |
— |
Read write |
The mode register load time parameter. This value is not used by the controller, as the controller derives the correct value from the memory type setting. |
|
23:16 |
tRAS |
— |
Read write |
The activate to precharge a timing parameter. The range of legal values is 4-29 cycles. |
|
31:24 |
tRC |
— |
Read write |
The activate to activate a timing parameter. The range of legal values is 8-40 cycles. |
|
0x124 |
3:0 |
tWTR |
— |
Read write |
The write to read a timing parameter. The range of legal values is 1-10 cycles. |
7:4 |
tRTP |
— |
Read write |
The read to precharge a timing parameter. The range of legal values is 2-8 cycles. |
|
15:8 |
tFAW |
— |
Read write |
The four-activate window timing parameter. The range of legal values is 6-32 cycles. |
|
31:16 |
Reserved. |
0 |
— |
Reserved for future use. |
|
0x125 |
15:0 |
tREFI |
— |
Read write |
The refresh interval timing parameter. The range of legal values is 780-6240 cycles. |
23:16 |
tRFC |
— |
Read write |
The refresh cycle timing parameter. The range of legal values is 12-255 cycles. |
|
31:24 |
Reserved. |
0 |
— |
Reserved for future use. |
|
0x126 |
3:0 |
Reserved. |
0 |
— |
Reserved for future use. |
7:4 |
Reserved. |
0 |
— |
Reserved for future use. |
|
11:8 |
Reserved. |
0 |
— |
Reserved for future use. |
|
15:12 |
Reserved. |
0 |
— |
Reserved for future use. |
|
23:16 |
Burst Length |
— |
Read write |
Value must match memory burst length. |
|
31:24 |
Reserved. |
0 |
— |
Reserved for future use. |
|
0x130 |
0 |
ENABLE_ECC |
1 |
Read write |
When this bit equals 1, it enables the generation and checking of ECC. This bit is only active if ECC was enabled during IP parameterization. |
1 |
ENABLE_AUTO_CORR |
— |
Read write |
When this bit equals 1, it enables auto-correction when a single-bit error is detected. |
|
2 |
GEN_SBE |
0 |
Read write |
When this bit equals 1, it enables the deliberate insertion of single-bit errors, bit 0, in the data written to memory. This bit is used only for testing purposes. |
|
3 |
GEN_DBE |
0 |
Read write |
When this bit equals 1, it enables the deliberate insertion of double-bit errors, bits 0 and 1, in the data written to memory. This bit is used only for testing purposes. |
|
4 |
ENABLE_INTR |
1 |
Read write |
When this bit equals 1, it enables the interrupt output. |
|
5 |
MASK_SBE_INTR |
0 |
Read write |
When this bit equals 1, it masks the single-bit error interrupt. |
|
6 |
MASK_DBE_INTR |
0 |
Read write |
When this bit equals 1, it masks the double-bit error interrupt |
|
7 |
CLEAR |
0 |
Read write |
When this bit equals 1, writing to this self-clearing bit clears the interrupt signal, and the error status and error address registers. |
|
8 |
MASK_CORDROP_INTR |
0 |
Read write |
When this bit equals 1, the dropped autocorrection error interrupt is dropped. |
|
9 |
Reserved. |
0 |
— |
Reserved for future use. |
|
0x131 |
0 |
SBE_ERROR |
0 |
Read only |
Set to 1 when any single-bit errors occur. |
1 |
DBE_ERROR |
0 |
Read only |
Set to 1 when any double-bit errors occur. |
|
2 |
CORDROP_ERROR |
0 |
Read only |
Value is set to 1 when any controller-scheduled autocorrections are dropped. |
|
7:3 |
Reserved. |
0 |
— |
Reserved for future use. |
|
15:8 |
SBE_COUNT |
0 |
Read only |
Reports the number of single-bit errors that have occurred since the status register counters were last cleared. |
|
23:16 |
DBE_COUNT |
0 |
Read only |
Reports the number of double-bit errors that have occurred since the status register counters were last cleared. |
|
31:24 |
CORDROP_COUNT |
0 |
Read only |
Reports the number of controller-scheduled autocorrections dropped since the status register counters were last cleared. |
|
0x132 |
31:0 |
ERR_ADDR |
0 |
Read only |
The address of the most recent ECC error. This address is a memory burst-aligned local address. |
0x133 |
31:0 |
CORDROP_ADDR |
0 |
Read only |
The address of the most recent autocorrection that was dropped. This is a memory burst-aligned local address. |
0x134 |
0 |
REORDER_DATA |
— |
Read write |
|
15:1 |
Reserved. |
0 |
— |
Reserved for future use. |
|
23:16 |
STARVE_LIMIT |
0 |
Read write |
Number of commands that can be served before a starved command. |
|
31:24 |
Reserved. |
0 |
— |
Reserved for future use. |