External Memory Interface Handbook Volume 3: Reference Material

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ID 683841
Date 7/24/2019
Public
Document Table of Contents

17.3. Resolving Port Name Differences

Several port names in the ALTMEMPHY datapath are different than in the UniPHY datapath. The different names may cause compilation errors.

This topic describes the changes you must make in the RTL for the entity that instantiates the memory IP core. Each change applies to a specific port in the ALTMEMPHY datapath. Unconnected ports require no changes.

In some instances, multiple ports in ALTMEMPHY-based designs are mapped to a single port in UniPHY-based designs. If you use both ports in ALTMEMPHY-based designs, assign a temporary signal to the common port and connect it to the original wires. The following table shows the changes you must make.

Table 138.  Changes to ALTMEMPHY Port Names

ALTMEMPHY Port

Changes

aux_full_rate_clk

The UniPHY-based design does not generate this signal. You can generate it if you require it.

aux_scan_clk

The UniPHY-based design does not generate this signal. You can generate it if you require it.

aux_scan_clk_reset_n

The UniPHY-based design does not generate this signal. You can generate it if you require it.

dll_reference_clk

The UniPHY-based design does not generate this signal. You can generate it if you require it.

dqs_delay_ctrl_export

This signal is for DLL sharing between ALTMEMPHY instances and is not applicable for UniPHY-based designs.

local_address

Rename to avl_addr.

local_be

Rename to avl_be.

local_burstbegin

Rename to avl_burstbegin.

local_rdata

Rename to avl_rdata.

local_rdata_valid

Rename to avl_rdata_valid.

local_read_req

Rename to avl_read_req.

local_ready

Rename to avl_ready.

local_size

Rename to avl_size.

local_wdata

Rename to avl_wdata.

local_write_req

Rename to avl_write_req.

mem_addr

Rename to mem_a.

mem_clk

Rename to mem_ck.

mem_clk_n

Rename to mem_ck_n.

mem_dqsn

Rename to mem_dqs_n.

oct_ctl_rs_value

Remove from design (see “Creating OCT Signals”).

oct_ctl_rt_value

Remove from design (see “Creating OCT Signals”).

phy_clk

Rename to afi_clk.

reset_phy_clk_n

Rename to afi_reset_n.

local_refresh_ack reset_request_n

The controller no longer exposes these signals to the top-level design, so comment out these outputs. If you need it, bring the wire out from the high-performance II controller entity in <project_directory>/<variation name>.v.

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