External Memory Interface Handbook Volume 3: Reference Material

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ID 683841
Date 7/24/2019
Public
Document Table of Contents

6.11. Port Mappings

The memory interface controller has a set of command, read data, and write data ports that support AXI3, AXI4 and Avalon-MM. Tables are provided to identify port assignments and functions.
Table 75.  Command Port Assignments

Command Port

Allowed Functions

0, 2, 4

FPGA fabric AXI read command ports

FPGA fabric Avalon-MM read or write command ports

1, 3, 5

FPGA fabric AXI write command ports

FPGA fabric Avalon-MM read or write command ports

6

L3 AXI read command port

7

MPU AXI read command port

8

L3 AXI write command port

9

MPU AXI write command port

Table 76.  Read Port Assignments

Read Port

Allowed Functions

0, 1, 2, 3

64-bit read data from the FPGA fabric. When 128-bit data read ports are created, then read data ports 0 and1 get paired as well as 2 and 3.

4

32-bit L3 read data port

5

64-bit MPU read data port

Table 77.  Write Port Assignments

Write Port

Allowed Functions

0, 1, 2, 3

64-bit write data from the FPGA fabric. When 128-bit data write ports are created, then write data ports 0 and 1 get paired as well as 2 and 3.

4

32-bit L3 write data port

5

64-bit MPU write data port

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