External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

12.4. Document Revision History

Date Version Changes
May 2017 2017.05.08
  • Retitled EMIF Configurable Traffic Generator 2.0 Reference to Testing the EMIF Interface Using the Traffic Generator 2.0.
  • Removed Configurable Traffic Generator Parameters section.
  • Consolidated Traffic Generator 2.0 usage information in External Memory Interface Debug Toolkit chapter.
  • Rebranded as Intel.
October 2016 2016.10.31 Maintenance release.
May 2016 2016.05.02
  • Modified step 6 of Compiling and Testing the Design in Hardware.
  • Added Configuring the Traffic Generator 2.0.
  • Added The Traffic Generator 2.0 Report.
  • Changed heading from EMIF Configurable Traffic Generator 2.0 for Arria 10 EMIF IP to EMIF Configurable Traffic Generator 2.0 Reference.
  • Added Bypass the traffic generator repeated-writes/ repeated-reads test pattern, Bypass the traffic generator stress pattern, and Export Traffic Generator 2.0 configuration interface to Configurable Traffic Generator Parameters table. Removed Number of Traffic Generator 2.0 configuration interfaces.
  • Added TG_WRITE_REPEAT_ COUNT, TG_READ_REPEAT_ COUNT, TG_DATA_MODE, and TG_BYTEEN_MODE to Configuration Options for Read/Write Generation table.
  • Added Error Report Register Bits table to Test Information section.
  • Corrected paths in Simulation and Hardware sections of Performing Your Own Tests Using Traffic Generator 2.0 topic.
November 2015 2015.11.02
  • Added EMIF Configurable Traffic Generator 2.0 for Arria 10 EMIF IP.
  • Added Arria 10 EMIF IP Example Design Quick Start Guide.
  • Changed order of sections in chapter.
  • Changed instances of Quartus II to Quartus Prime.
May 2015 2015.05.04 Maintenance release.
December 2014 2014.12.15 Maintenance release.
August 2014 2014.08.15 Removed occurrence of MegaWizard Plug-In Manager.
December 2013 2013.12.16 Removed references to SOPC Builder.
November 2012 1.3
  • Added block diagrams of simulation and synthesis example designs for RLDRAM 3 and Ping Pong PHY.

  • Changed chapter number from 7 to 9.
June 2012 1.2 Added Feedback icon.
November 2011 1.1
  • Added Synthesis Example Design and Simulation Example Design sections.
  • Added Creating and Connecting the UniPHY Memory Interface and the Traffic Generator in Qsys.

  • Revised Example Driver section as Traffic Generator and BIST Engine.

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