External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

15.3. QDR II and QDR II+ Timing Diagrams

This topic contains timing diagrams for UniPHY-based external memory interface IP for QDR II and QDR II+ protocols.

The following figures present timing diagrams, based on a Stratix III device:

Figure 191. Half-Rate QDR II and QDR II+ SRAM Read


Notes for the above Figure:

  1. Controller receives read command.
  2. Controller issues two read commands to PHY.
  3. PHY issues two read commands to memory.
  4. PHY receives read data from memory.
  5. Controller receives read data from PHY.
  6. User logic receives read data from controller.
Figure 192. Half-Rate QDR II and QDR II+ SRAM Write


Notes for the above Figure:

  1. Controller receives write command.
  2. Controller receives write data.
  3. Controller issues two write commands to PHY.
  4. Controller sends write data to PHY.
  5. PHY issues two write commands to memory.
  6. PHY sends write data to memory.
Figure 193. Full-Rate QDR II and QDR II+ SRAM Read


Notes for the above Figure:

  1. Controller receives read command.
  2. Controller issues two read commands to PHY.
  3. PHY issues two read commands to memory.
  4. PHY receives read data from memory.
  5. Controller receives read data from PHY.
  6. User logic receives read data from controller.
Figure 194. Full-Rate QDR II and QDR II+ SRAM Write


Notes for the above Figure:

  1. Controller receives write command.
  2. Controller receives write data.
  3. Controller issues two write commands to PHY.
  4. Controller sends write data to PHY.
  5. PHY issues two write commands to memory.
  6. PHY sends write data to memory.

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