External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

12.3.4. Creating and Connecting the UniPHY Memory Interface and the Traffic Generator in Qsys

The traffic generator can be used in Qsys as a stand-alone component for use within a larger system.

To create the system in Qsys, perform the following steps:

  1. Start Qsys.
  2. On the Project Settings tab, select the required device from the Device Family list.
  3. In the Component Library, choose a UniPHY memory interface to instantiate. For example, under Library > Memories and Memory Controllers > External Memory Interfaces, select DDR3 SDRAM Controller with UniPHY.
  4. Configure the parameters for your instantiation of the memory interface.
  5. In the Component Library, find the example driver and instantiate it in the system. For example, under Library > Memories and Memory Controllers > Pattern Generators, select Avalon-MM Traffic Generator and BIST Engine.
  6. Configure the parameters for your instantiation of the example driver.
    Note: The Avalon specification stipulates that Avalon-MM master interfaces issue byte addresses, while Avalon-MM slave interfaces accept word addresses. The default for the Avalon-MM Traffic Generator and BIST Engine is to issue word addresses. When using Qsys, you must enable the Generate per byte address setting in the traffic generator.
  7. Connect the interfaces as illustrated in the following figure. At this point, you can generate synthesis RTL, Verilog or VHDL simulation RTL, or a simulation testbench system.

    Qsys System

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