External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Document Table of Contents

7.3.9. ECC

The ECC logic comprises an encoder and a decoder-corrector, which can detect and correct single-bit errors, and detect double-bit errors. The ECC logic is available in multiples of 16, 24, 40, and 72 bits.
Note: For the hard memory controller with multiport front end available in Arria V and Cyclone V devices, ECC logic is limited to widths of 24 and 40.
  • The ECC logic has the following features:
  • Has Hamming code ECC logic that encodes every 64, 32, 16, or 8 bits of data into 72, 40, 24, or 16 bits of codeword.
  • Has a latency increase of one clock for both writes and reads.
  • For a 128-bit interface, ECC is generated as one 64-bit data path with 8-bits of ECC path, plus a second 64-bit data path with 8-bits of ECC path.
  • Detects and corrects all single-bit errors.
  • Detects all double-bit errors.
  • Counts the number of single-bit and double-bit errors.
  • Accepts partial writes, which trigger a read-modify-write cycle, for memory devices with DM pins.
  • Can inject single-bit and double-bit errors to trigger ECC correction for testing and debugging purposes.
  • Generates an interrupt signal when an error occurs.
Note: When using ECC, you must initialize your entire memory content to zero before beginning to write to the memory. If you do not initialize the content to zero, and if you read from uninitialized memory locations without having first written to them, you will see junk data which will trigger an ECC interrupt.

When a single-bit or double-bit error occurs, the ECC logic triggers the ecc_interrupt signal to inform you that an ECC error has occurred. When a single-bit error occurs, the ECC logic reads the error address, and writes back the corrected data. When a double-bit error occurs, the ECC logic does not do any error correction but it asserts the avl_rdata_error signal to indicate that the data is incorrect. The avl_rdata_error signal follows the same timing as the avl_rdata_valid signal.

Enabling autocorrection allows the ECC logic to delay all controller pending activities until the correction completes. You can disable autocorrection and schedule the correction manually when the controller is idle to ensure better system efficiency. To manually correct ECC errors, follow these steps:

  1. When an interrupt occurs, read out the SBE_ERROR register. When a single-bit error occurs, the SBE_ERROR register is equal to one.
  2. Read out the ERR_ADDR register.
  3. Correct the single-bit error by issuing a dummy write to the memory address stored in the ERR_ADDR register. A dummy write is a write request with the local_be signal zero, that triggers a partial write which is effectively a read-modify-write event. The partial write corrects the data at that address and writes it back.

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