External Memory Interface Handbook Volume 3: Reference Material

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ID 683841
Date 7/24/2019
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7.3.7. ODT Generation Logic

The on-die termination (ODT) generation logic generates the necessary ODT signals for the controller, based on the scheme that Intel recommends.

DDR2 SDRAM

Note: There is no ODT for reads.
Table 82.  ODT—DDR2 SDRAM Single Slot Single Chip-select Per DIMM (Write)

Write On

ODT Enabled

mem_cs[0]

mem_odt [0]

Note: There is no ODT for reads.
Table 83.  ODT—DDR2 SDRAM Single Slot Dual Chip-select Per DIMM (Write)

Write On

ODT Enabled

mem_cs[0]

mem_odt [0]

mem_cs[1]
mem_odt[1]
Table 84.  ODT—DDR2 SDRAM Dual Slot Single Chip-select Per DIMM (Write)

Write On

ODT Enabled

mem_cs[0]

mem_odt [1]

mem_cs[1]
mem_odt[0]
Table 85.  ODT—DDR2 SDRAM Dual Slot Dual Chip-select Per DIMM (Write)

Write On

ODT Enabled

mem_cs[0]
mem_odt[2]
mem_cs[1]
mem_odt[3]
mem_cs[2]
mem_odt[0]
mem_cs[3]
mem_odt[1]

DDR3 SDRAM

Note: There is no ODT for reads.
Table 86.  ODT—DDR3 SDRAM Single Slot Single Chip-select Per DIMM (Write)

Write On

ODT Enabled

mem_cs[0]

mem_odt [0]

Note: There is no ODT for reads.
Table 87.  ODT—DDR3 SDRAM Single Slot Dual Chip-select Per DIMM (Write)

Write On

ODT Enabled

mem_cs[0]

mem_odt [0]

mem_cs[1]
mem_odt[1]
Table 88.  ODT—DDR3 SDRAM Dual Slot Single Chip-select Per DIMM (Write)

Write On

ODT Enabled

mem_cs[0]

mem_odt [0] and mem_odt [1]

mem_cs[1]

mem_odt [0] and mem_odt [1]

Table 89.  ODT—DDR3 SDRAM Dual Slot Single Chip-select Per DIMM (Read)

Read On

ODT Enabled

mem_cs[0]
mem_odt[1]
mem_cs[1]
mem_odt[0]
Table 90.  ODT—DDR3 SDRAM Dual Slot Dual Chip-select Per DIMM (Write)

Write On

ODT Enabled

mem_cs[0]

mem_odt [0] and mem_odt [2]

mem_cs[1]

mem_odt [1]and mem_odt [3]

mem_cs[2]

mem_odt [0]and mem_odt [2]

mem_cs[3]

mem_odt [1]and mem_odt [3]

Table 91.  ODT—DDR3 SDRAM Dual Slot Dual Rank Per DIMM (Read)

Read On

ODT Enabled

mem_cs[0]
mem_odt[2]
mem_cs[1]
mem_odt[3]
mem_cs[2]
mem_odt[0]
mem_cs[3]
mem_odt[1]

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