External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

14.4. QDR II and QDR II+ SRAM Latency

The following table shows the latency in full-rate memory clock cycles.

Table 133.  QDR II Latency (In Full-Rate Memory Clock Cycles)  (1)

Latency in Full-Rate Memory Clock Cycles

Rate

Controller Address & Command

PHY Address & Command

Memory Maximum Read

PHY Read Return

Controller Read Return

Round Trip

Round Trip Without Memory

Half 1.5 RL

2

5.5

1.5

7.0

0

16

14.5

Half 2.0 RL

2

5.5

2.0

6.5

0

16

14.0

Half 2.5 RL

2

5.5

2.5

6.0

0

16

13.5

Full 1.5 RL

2

1.5

1.5

4.0

1

10

8.5

Full 2.0 RL

2

1.5

2.0

4.5

1

11

9.0

Full 2.5 RL

2

1.5

2.5

4.0

1

11

8.5

Note to Table:

  1. RL = Read latency

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