External Memory Interface Handbook Volume 3: Reference Material

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ID 683841
Date 7/24/2019
Public
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1.15.2.1. Ping Pong Gasket

The gasket delays and remaps quarter-rate signals so that they are correctly time-multiplexed at the full-rate PHY output. The gasket also merges address and command buses ahead of the PHY.

AFI interfaces at the input and output of the gasket provide compatibility with the PHY and with memory controllers.

Figure 22. Ping Pong PHY Gasket Architecture


The following table shows how the gasket processes key AFI signals.

Table 17.  Key AFI Signals Processed by Ping Pong PHY Gasket

Signal

Direction(Width multiplier)

Description

Gasket Conversions

cas, ras, we, addr, ba

Controller (1x) to PHY (1x)

Address and command buses shared between devices.

Delay RHS by 1T; merge.

cs, odt, cke

Controller (1x) to PHY (2x)

Chip select, on-die termination, and clock enable, one per device.

Delay RHS by 1T; reorder, merge.

wdata, wdata_valid, dqs_burst, dm

Controller (1x) to PHY (2x)

Write datapath signals, one per device.

Delay RHS by 1T; reorder, merge.

rdata_en_rd, rdata_en_rd_full

Controller (1x) to PHY (2x)

Read datapath enable signals indicating controller performing a read operation, one per device.

Delay RHS by 1T.

rdata_rdata_valid

PHY (2x) to Controller (1x)

Read data, one per device.

Reorder; split.

cal_fail, cal_success, seq_busy, wlat, rlat

PHY (1x) to Controller (1x)

Calibration result, one per device.

Pass through.

rst_n, mem_clk_disable, ctl_refresh_done, ctl_long_idle

Controller (1x) to PHY (1x)

Reset and DQS tracking signals, one per PHY.

AND (&)

cal_req, init_req

Controller (1x) to PHY (1x)

Controller to sequencer requests.

OR (|)

wrank, rrank

Controller (1x) to PHY (2x)

Shadow register support.

Delay RHS by 1T; reorder; merge.

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