External Memory Interface Handbook Volume 3: Reference Material

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ID 683841
Date 7/24/2019
Public
Document Table of Contents

14.1. DDR2 SDRAM LATENCY

The following table shows the DDR2 SDRAM latency in full-rate memory clock cycles.

Table 130.  DDR2 SDRAM Controller Latency (In Full-Rate Memory Clock Cycles) (1) (2)

Latency in Full-Rate Memory Clock Cycles

Rate

Controller Address & Command

PHY Address & Command

Memory Maximum Read

PHY Read Return

Controller Read Return

Round Trip

Round Trip Without Memory

Half

10

EWL: 3

3–7

6

4

EWL: 26–30

EWL: 23

OWL: 4

OWL: 27–31

OWL: 24

Full

5

0

3–7

4

10

22–26

19

Notes to Table:

  1. EWL = Even write latency
  2. OWL = Odd write latency

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