External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
Document Table of Contents

14.4. Creating OCT Signals

In ALTMEMPHY-based designs, the Quartus Prime Fitter creates the alt_oct block outside the IP core and connects it to the oct_ctl_rs_value and oct_ctl_rt_value signals.

In UniPHY-based designs, the OCT block is part of the IP core, so the design no longer requires these two ports. Instead, the UniPHY-based design requires two additional ports, oct_rup and oct_rdn (for Stratix III and Stratix IV devices), or oct_rzqin (for Stratix V devices). You must create these ports in the instantiating entity as input pins and connect to the UniPHY instance. Then route these pins to the top-level design and connect to the OCT RUP and RDOWN resistors on the board.

For information on OCT control block sharing, refer to “The OCT Sharing Interface” in this volume.