External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Document Table of Contents

1.18. Document Revision History

Date Version Changes
May 2017 2017.05.08 Rebranded as Intel.
October 2016 2016.10.31
  • Changed Note 3 to the Word-Aligned Writes figure, in the PHY-to-Controller Interfaces topic.
May 2016 2016.05.02
  • Added statement that Efficiency Monitor and Protocol checker is not available for QDR II and QDR II+ SRAM, or for the MAX 10 device family, or for Arria V or Cyclone V designs using the Hard Memory Controller, to Efficiency Monitor and Protocol Checker topic.
November 2015 2015.11.02
  • Replaced the AFI 4.0 Specification with the AFI 3.0 Specification.
  • Replaced instances of Quartus II with Quartus Prime.
May 2015 2015.05.04 Maintenance release.
December 2014 2014.12.15
  • Added several parameters to the AFI Specification section:
  • Added several signals to the AFI Specification section:
    • afi_addr
    • afi_bg
    • afi_c_n
    • afi_rw_n
    • afi_act_n
    • afi_par
    • afi_alert_n
    • afi_ainv
    • afi_dinv
  • Changed the Width information for several signals in the AFI Specification section:
    • afi_dqs_burst
    • afi_wdata_valid
    • afi_stl_refresh_done
    • afi_seq_busy
    • afi_ctl_long_idle
August 2014 2014.08.15
  • Added note about 32-bit word addresses to Register Maps and UniPHY Register Map tables.
  • Changed register map information for address 0x004, bit 26, in UniPHY Register Map table.
December 2013 2013.12.16
  • Removed references to HardCopy.
  • Removed DLL Offset Control Block.
  • Removed references to SOPC Builder.
  • Increased minimum recommended pulse width for global_reset_n signal to 100ns.
  • Corrected terminology inconsistency.
  • Added information explaining PVT compensation.
  • Added quarter-rate information to PHY-to-Controller Interfaces section.
  • Expanded descriptions of INIT_FAILING_STAGE and INIT_FAILING_SUBSTAGE in UniPHY Register map.
  • Added footnote about afi_rlat signal to Calibration Status Signals table.
November 2012 3.1
  • Moved Controller Register Map to Functional Description—HPC II Controller chapter.
  • Updated Sequencer States information in Table 1–2.
  • Enhanced Using a Custom Controller information.
  • Enhanced Tracking Manager information.
  • Added Ping Pong PHY information.
  • Added RLDRAM 3 support.
  • Added LRDIMM support.
  • Added Arria V GZ support.
June 2012 3.0
  • Added Shadow Registers section.
  • Added LPDDR2 support.
  • Added new AFI signals.
  • Added Calibration Time section.
  • Added Feedback icon.
November 2011 2.1
  • Consolidated UniPHY information from 11.0 DDR2 and DDR3 SDRAM Controller with UniPHY User Guide, QDR II and QDR II+ SRAM Controller with UniPHY User Guide, and RLDRAM II Controller with UniPHY IP User Guide.

  • Revised Reset and Clock Generation and Dedicated Clock Networks sections.
  • Revised Figure 1–3 and Figure 1–5.
  • Added Tracking Manager to Sequencer section.
  • Revised Interfaces section for DLL, PLL, and OCT sharing interfaces.
  • Revised Using a Custom Controller section.
  • Added UniPHY Calibration Stages section; reordered stages 3 and 4, removed stage 5.

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