||Rebranded as Intel.
- Changed Note 3 to the Word-Aligned Writes figure, in the PHY-to-Controller Interfaces topic.
- Added statement that Efficiency Monitor and Protocol checker is not available for QDR II and QDR II+ SRAM, or for the MAX 10 device family, or for Arria V or Cyclone V designs using the Hard Memory Controller, to Efficiency Monitor and Protocol Checker topic.
- Replaced the AFI 4.0 Specification with the AFI 3.0 Specification.
- Replaced instances of Quartus II with Quartus Prime.
- Added several parameters to the AFI Specification section:
- Added several signals to the AFI Specification section:
- Changed the Width information for several signals in the AFI Specification section:
- Added note about 32-bit word addresses to Register Maps and UniPHY Register Map tables.
- Changed register map information for address 0x004, bit 26, in UniPHY Register Map table.
- Removed references to HardCopy.
- Removed DLL Offset Control Block.
- Removed references to SOPC Builder.
- Increased minimum recommended pulse width for global_reset_n signal to 100ns.
- Corrected terminology inconsistency.
- Added information explaining PVT compensation.
- Added quarter-rate information to PHY-to-Controller Interfaces section.
- Expanded descriptions of INIT_FAILING_STAGE and INIT_FAILING_SUBSTAGE in UniPHY Register map.
- Added footnote about afi_rlat signal to Calibration Status Signals table.
- Moved Controller Register Map to Functional Description—HPC II Controller chapter.
- Updated Sequencer States information in Table 1–2.
- Enhanced Using a Custom Controller information.
- Enhanced Tracking Manager information.
- Added Ping Pong PHY information.
- Added RLDRAM 3 support.
- Added LRDIMM support.
- Added Arria V GZ support.
- Added Shadow Registers section.
- Added LPDDR2 support.
- Added new AFI signals.
- Added Calibration Time section.
- Added Feedback icon.
Consolidated UniPHY information from 11.0 DDR2 and DDR3 SDRAM Controller with UniPHY User Guide, QDR II and QDR II+ SRAM Controller with UniPHY User Guide, and RLDRAM II Controller with UniPHY IP User Guide.
- Revised Reset and Clock Generation and Dedicated Clock Networks sections.
- Revised Figure 1–3 and Figure 1–5.
- Added Tracking Manager to Sequencer section.
- Revised Interfaces section for DLL, PLL, and OCT sharing interfaces.
- Revised Using a Custom Controller section.
- Added UniPHY Calibration Stages section; reordered stages 3 and 4, removed stage 5.