External Memory Interface Handbook Volume 3: Reference Material

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ID 683841
Date 7/24/2019
Public
Document Table of Contents

1.7.2. RTL-based Sequencer

The RTL-based sequencer is available for QDR II and RLDRAM II interfaces, on supported device families other than Arria V. The RTL sequencer is a state machine that processes the calibration algorithm.

The sequencer assumes control of the interface at reset (whether at initial startup or when the IP is reset) and maintains control throughout the calibration process. The sequencer relinquishes control to the memory controller only after successful calibration. The following tables list the major states in the RTL-based sequencer.

Table 2.  Sequencer States

RTL-based Sequencer State

Description

RESET

Remain in this state until reset is released.

LOAD_INIT

Load any initialization values for simulation purposes.

STABLE

Wait until the memory device is stable.

WRITE_ZERO

Issue write command to address 0.

WAIT_WRITE_ZERO

Write all 0xAs to address 0.

WRITE_ONE

Issue write command to address 1.

WAIT_WRITE_ONE

Write all 0x5s to address 1.

Valid Calibration States

V_READ_ZERO

Issue read command to address 0 (expected data is all 0xAs).

V_READ_NOP

This state represents the minimum number of cycles required between 2 back-to-back read commands. The number of NOP states depends on the burst length.

V_READ_ONE

Issue read command to address 1 (expected data is all 0x5s).

V_WAIT_READ

Wait for read valid signal.

V_COMPARE_READ_ZERO_READ_ONE

Parameterizable number of cycles to wait before making the read data comparisons.

V_CHECK_READ_FAIL

When a read fails, the write pointer (in the AFI clock domain) of the valid FIFO buffer is incremented. The read pointer of the valid FIFO buffer is in the DQS clock domain. The gap between the read and write pointers is effectively the latency between the time when the PHY receives the read command and the time valid data is returned to the PHY.

V_ADD_FULL_RATE

Advance the read valid FIFO buffer write pointer by an extra full rate cycle.

V_ADD_HALF_RATE

Advance the read valid FIFO buffer write pointer by an extra half rate cycle. In full-rate designs, equivalent to V_ADD_FULL_RATE.

V_READ_FIFO_RESET

Reset the read and write pointers of the read data synchronization FIFO buffer.

V_CALIB_DONE

Valid calibration is successful.

Latency Calibration States

L_READ_ONE

Issue read command to address 1 (expected data is all 0x5s).

L_WAIT_READ

Wait for read valid signal from read datapath. Initial read latency is set to a predefined maximum value.

L_COMPARE_READ_ONE

Check returned read data against expected data. If data is correct, go to L_REDUCE_LATENCY; otherwise go to L_ADD_MARGIN.

L_REDUCE_LATENCY

Reduce the latency counter by 1.

L_READ_FLUSH

Read from address 0, to flush the contents of the read data resynchronization FIFO buffer.

L_WAIT_READ_FLUSH

Wait until the whole FIFO buffer is flushed, then go back to L_READ and try again.

L_ADD_MARGIN

Increment latency counter by 3 (1 cycle to get the correct data, 2 more cycles of margin for run time variations). If latency counter value is smaller than predefined ideal condition minimum, then go to CALIB_FAIL.

CALIB_DONE

Calibration is successful.

CALIB_FAIL

Calibration is not successful.

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