External Memory Interface Handbook Volume 3: Reference Material

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ID 683841
Date 7/24/2019
Public
Document Table of Contents

7.4.3.2. AXI Interface Parameters

Table 92.  AXI Interface Parameters

Parameter Name

Description / Value

AXI_ID_WIDTH

Width of the AXI ID bus. Default value is 4.

AXI_ADDR_WIDTH

Width of the AXI address bus. Must be set according to the Avalon interface address and data bus width as shown below:AXI_ADDR_WIDTH = LOCAL_ADDR_WIDTH + log2(LOCAL_DATA_WIDTH/8)LOCAL_ADDR_WIDTH is the memory controller Avalon interface address width.LOCAL_DATA_WIDTH is the memory controller Avalon data interface width.

AXI_LEN_WIDTH

Width of the AXI length bus. Default value is 8. Should be set to LOCAL_SIZE_WIDTH - 1, where LOCAL_SIZE_WIDTH is the memory controller Avalon interface burst size width

AXI_SIZE_WIDTH

Width of the AXI size bus. Default value is 3.

AXI_BURST_WIDTH

Width of the AXI burst bus. Default value is 2.

AXI_LOCK_WIDTH

Width of the AXI lock bus. Default value is 2.

AXI_CACHE_WIDTH

Width of the AXI cache bus. Default value is 4.

AXI_PROT_WIDTH

Width of the AXI protection bus. Default value is 3.

AXI_DATA_WIDTH

Width of the AXI data bus. Should be set to match the Avalon interface data bus width.AXI_DATA_WIDTH = LOCAL_DATA_WIDTH, where LOCAL_DATA_WIDTH is the memory controller Avalon interface input data width.

AXI_RESP_WIDTH

Width of the AXI response bus. Default value is 2.

ST_ADDR_WIDTH

Width of the Avalon interface address. Must be set to match the Avalon interface address bus width.ST_ADDR_WIDTH = LOCAL_ADDR_WIDTH, where LOCAL_ADDR_WIDTH is the memory controller Avalon interface address width.

ST_SIZE_WIDTH

Width of the Avalon interface burst size.ST_SIZE_WIDTH = AXI_LEN_WIDTH + 1

ST_ID_WIDTH

Width of the Avalon interface ID. Default value is 4.ST_ID_WIDTH = AXI_ID_WIDTH

ST_DATA_WIDTH

Width of the Avalon interface data.ST_DATA_WIDTH = AXI_DATA_WIDTH.

COMMAND_ARB_TYPE

Specifies the AXI command arbitration type, as shown:ROUND_ROBIN: arbitrates between read and write address channel in round robin fashion. Default option.WRITE_PRIORITY: write address channel has priority if both channels send request simultaneously.READ_PRIORITY: read address channel has priority if both channels send request simultaneously.

REGISTERED

Setting this parameter to 1 adds an extra register stage in the AXI interface and incurs one extra clock cycle of latency. Default value is 1.

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