External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

14.3. LPDDR2 SDRAM LATENCY

The following table shows the LPDDR2 SDRAM latency in full-rate memory clock cycles.

Table 132.  LPDDR2 SDRAM Controller Latency (In Full-Rate Memory Clock Cycles)  (1) (2) (3) (4)

Latency in Full-Rate Memory Clock Cycles

Rate

Controller Address & Command

PHY Address & Command

Memory Maximum Read

PHY Read Return

Controller Read Return

Round Trip

Round Trip Without Memory

Half

10

EWER: 3

5–11

EWER: 7

4

EWER: 29–35

EWER: 24

EWOR: 3

EWOR: 6

EWOR: 28–34

EWOR: 23

OWER: 4

OWER: 6

OWER: 29–35

OWER: 24

OWOR: 4

OWOR: 7

OWOR: 30–36

OWOR: 25

Full

5

0

5–11

4

10

24–30

19

Notes to Table:

  1. EWER = Even write latency and even read latency
  2. EWOR = Even write latency and odd read latency
  3. OWER = Odd write latency and even read latency
  4. OWOR = Odd write latency and odd read latency

Did you find the information on this page useful?

Characters remaining:

Feedback Message