External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

13.4. UniPHY-Based External Memory Interface Features

The following table summarizes key feature support for Intel® ’s UniPHY-based external memory interfaces.
Table 119.  Feature Support  

Key Feature

Protocol

DDR2

DDR3

LPDDR2

QDR II

RLDRAM II

RLDRAM 3

High-performance controller II (HPC II)

Yes

Yes

Yes

Half-rate core logic and user interface

Yes

Yes

Yes

Yes

Yes

Yes

Full-rate core logic and user interface

Yes

Yes

Yes

Quarter-rate core logic and user interface

Yes (1)

Yes

Dynamically generated Nios II-based sequencer

Yes

Yes

Yes

Yes

Yes

Yes

Choice of RTL-based or dynamically generated Nios® II-based sequencer

Yes (2) (3) (12)

Yes

(12)

Available Efficiency Monitor and Protocol Checker (14)

Yes

Yes

Yes

Yes

Yes

DDR3L support

Yes (13)

UDIMM and RDIMM in any form factor

Yes

Yes (4) (5)

Multiple components in a single-rank UDIMM or RDIMM layout

Yes

Yes

LRDIMM

Yes

Burst length (half-rate)

8

8 or 16

4

4 or 8

2, 4, or 8

Burst length (full-rate)

4

2 or 4

2, 4, or 8

Burst length (quarter-rate)

8

2, 4, or 8

Burst length of 8 and burst chop of 4 (on the fly)

Yes

With leveling

240 MHz and above (10)

Yes (9) (10)

Yes

Without leveling

Below 240 MHz

Yes

Maximum data width

144 bits (6)

144 bits (6)

32 bits

72 bits

72 bits

72 bits

Reduced controller latency

Yes (2) (7)

Yes (2) (7)

Read latency

1.5 (QDR II) 2 or 2.5 (QDR II+)

ODT (in memory device)

Yes

QDR II+ only

Yes

Yes

x36 emulation mode

Yes (8) (10)

Notes:

  1. For Arria V, Arria V GZ, and Stratix V devices only.
  2. Not available in Arria II GX devices.
  3. Nios II-based sequencer not available for full-rate interfaces.
  4. For DDR3, the DIMM form is not supported in Arria II GX, Arria II GZ, Arria V, or Cyclone V devices.
  5. Arria II GZ uses leveling logic for discrete devices in DDR3 interfaces to achieve high speeds, but that leveling cannot be used to implement the DIMM form in DDR3 interfaces.
  6. For any interface with data width above 72 bits, you must use software timing analysis of your complete design to determine the maximum clock rate.
  7. The maximum achievable clock rate when reduced controller latency is selected must be attained through Quatrus Prime software timing analysis of your complete design.
  8. Emulation mode allows emulation of a larger memory-width interface using multiple smaller memory-width interfaces. For example, an x36 QDR II or QDR II+ interface can be emulated using two x18 interfaces.
  9. The leveling delay on the board between first and last DDR3 SDRAM component laid out as a DIMM must be less than 0.69 tCK.
  10. Leveling is not available for Arria V or Cyclone V devices.
  11. x36 emulation mode is not supported in Arria V, Arria V GZ, Cyclone V, or Stratix V devices.
  12. The RTL-based sequencer is not available for QDR II or RLDRAM II interfaces on Arria V devices.
  13. For Arria V, Arria V GZ, Cyclone V, and Stratix V.
  14. The Efficiency Monitor and Protocol Checker is is not available for QDR II and QDR II+ SRAM, or for the MAX 10 device family, or for Arria V or Cyclone V designs using the Hard Memory Controller.

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