External Memory Interface Handbook Volume 3: Reference Material

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ID 683841
Date 7/24/2019
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13.7.3. DDR2 and DDR3 Resource Utilization in Stratix III Devices

The following table shows typical resource usage of the DDR2 and DDR3 SDRAM controllers with UniPHY in the current version of Quartus Prime software for Stratix III devices.
Table 122.  Resource Utilization in Stratix III Devices  

Protocol

Memory Width (Bits)

Combinational ALUTS

Logic Registers

Mem ALUTs

M9K Blocks

M144K Blocks

Memory (Bits)

Controller

DDR2 (Half rate)

8

1,807

1,058

0

4

0

4,464

16

1,809

1,058

0

6

0

8,816

64

1,810

1,272

10

14

0

32,256

72

1,842

1,090

10

17

0

39,168

DDR2 (Full rate)

8

1,856

1,093

0

4

0

2,288

16

1,855

1,092

0

4

0

4,464

64

1,841

1,092

0

10

0

17,520

72

1,834

1,092

0

11

0

19,696

DDR3 (Half rate)

8

1,861

1,083

0

4

0

4,464

16

1,863

1,083

0

6

0

8,816

64

1,878

1,295

10

14

0

32,256

72

1,895

1,115

10

17

0

39,168

PHY

DDR2 (Half rate)

8

2,591

2,100

218

6

1

157,696

16

2,762

2,320

218

6

1

157,696

64

3,672

3,658

242

6

1

157,696

72

3,814

3,877

242

6

1

157,696

DDR2 (Full rate)

8

2,510

1,986

200

6

1

157,696

16

2,666

2,200

200

6

1

157,696

64

3,571

3,504

224

6

1

157,696

72

3,731

3,715

224

6

1

157,696

DDR3 (Half rate)

8

2,591

2,094

224

6

1

157,696

16

2,765

2,314

224

6

1

157,696

64

3,680

3,653

248

6

1

157,696

72

3,819

3,871

248

6

1

157,696

Total

DDR2 (Half rate)

8

4,398

3,158

218

10

1

162,160

16

4,571

3,378

218

12

1

166,512

64

5,482

4,930

252

20

1

189,952

72

5,656

4,967

252

23

1

196,864

DDR2 (Full rate)

8

4,366

3,079

200

10

1

159,984

16

4,521

3,292

200

10

1

162,160

64

5,412

4,596

224

16

1

175,216

72

5,565

4,807

224

17

1

177,392

DDR3 (Half rate)

8

4,452

3,177

224

10

1

162,160

16

4,628

3,397

224

12

1

166,512

64

5,558

4,948

258

20

1

189,952

72

5,714

4,986

258

23

1

196,864

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