Visible to Intel only — GUID: hco1416492530953
Ixiasoft
Visible to Intel only — GUID: hco1416492530953
Ixiasoft
1.16.5. Avalon® CSR Slave and JTAG Memory Map
Prior to reading the data in the CSR, you must issue a read command to address 0x01 to take a snapshot of the current data.
Address |
Bit |
Name |
Default |
Access |
Description |
---|---|---|---|---|---|
0x01 |
31:0 |
Reserved |
0 |
Read Only |
Used internally by EMIF Toolkit to identify Efficiency Monitor type. This address must be read prior to reading the other CSR contents. |
0x02 |
31:0 |
Reserved |
0 |
— |
Used internally by EMIF Toolkit to identify Efficiency Monitor version. |
0x08 |
0 |
Efficiency Monitor reset |
— |
Write only |
Write a 0 to reset. |
7:1 |
Reserved |
— |
— |
Reserved for future use. |
|
8 |
Protocol Checker reset |
— |
Write only |
Write a 0 to reset. |
|
15:9 |
Reserved |
— |
— |
Reserved for future use. |
|
16 |
Start/stop Efficiency Monitor |
— |
Read/Write |
Starting and stopping statistics gathering. |
|
23:17 |
Reserved |
— |
— |
Reserved for future use. |
|
31:24 |
Efficiency Monitor status |
— |
Read Only |
bit 0: Efficiency Monitor stopped bit 1: Waiting for start of pattern bit 2: Running bit 3: Counter saturation |
|
0x10 |
15:0 |
Efficiency Monitor address width |
— |
Read Only |
Address width of the Efficiency Monitor. |
31:16 |
Efficiency Monitor data width |
— |
Read Only |
Data Width of the Efficiency Monitor. |
|
0x11 |
15:0 |
Efficiency Monitor byte enable |
— |
Read Only |
Byte enable width of the Efficiency Monitor. |
31:16 |
Efficiency Monitor burst count width |
— |
Read Only |
Burst count width of the Efficiency Monitor. |
|
0x14 |
31:0 |
Cycle counter |
— |
Read Only |
Clock cycle counter for the Efficiency Monitor. Lists the number of clock cycles elapsed before the Efficiency Monitor stopped. |
0x18 |
31:0 |
Transfer counter |
— |
Read Only |
Counts any read or write data transfer cycle. |
0x1C |
31:0 |
Write counter |
— |
Read Only |
Counts write requests, including those during bursts. |
0x20 |
31:0 |
Read counter |
— |
Read Only |
Counts read requests. |
0x24 |
31:0 |
Readtotal counter |
— |
Read Only |
Counts read requests (total burst requests). |
0x28 |
31:0 |
NTC waitrequest counter |
— |
Read Only |
Counts Non Transfer Cycles (NTC) due to slave wait request high. |
0x2C |
31:0 |
NTC noreaddatavalid counter |
— |
Read Only |
Counts Non Transfer Cycles (NTC) due to slave not having read data. |
0x30 |
31:0 |
NTC master write idle counter |
— |
Read Only |
Counts Non Transfer Cycles (NTC) due to master not issuing command, or pause in write burst. |
0x34 |
31:0 |
NTC master idle counter |
— |
Read Only |
Counts Non Transfer Cycles (NTC) due to master not issuing command anytime. |
0x40 |
31:0 |
Read latency min |
— |
Read Only |
The lowest read latency value. |
0x44 |
31:0 |
Read latency max |
— |
Read Only |
The highest read latency value. |
0x48 |
31:0 |
Read latency total [31:0] |
— |
Read Only |
The lower 32 bits of the total read latency. |
0x49 |
31:0 |
Read latency total [63:32] |
— |
Read Only |
The upper 32 bits of the total read latency. |
0x50 |
7:0 |
Illegal command |
— |
Read Only |
Bits used to indicate which illegal command has occurred. Each bit represents a unique error. |
31:8 |
Reserved |
— |
— |
Reserved for future use. |