External Memory Interface Handbook Volume 3: Reference Material

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ID 683841
Date 7/24/2019
Public
Document Table of Contents

6.6.4.9. Example of Configuration for TrustZone

For a TrustZone® configuration, memory is TrustZone® divided into a range of memory accessible by secure masters and a range of memory accessible by non-secure masters. The two memory address ranges may have a range of memory that overlaps.

This example implements the following memory configuration:

  • 2 GB total RAM size
  • 0—512 MB dedicated secure area
  • 513—576 MB shared area
  • 577—2048 MB dedicated non-secure area
Figure 153. Example Memory Configuration


In this example, each port is configured by default to disallow all accesses. The following table shows the two rules programmed into the memory protection table.

Table 72.  Rules in Memory Protection Table for Example Configuration 

Rule #

Port Mask

AxID Low

AxID High

Address Low

Address High

protruledata.security

Fail/Allow

1

0x3FF (1023)

0x000

0xFFF (4095)

0

576

0x1

Allow

2

0x3FF (1023)

0x000

0xFFF (4095)

512

2047

0x0

Allow

The port mask value, AxID Low, and AxID High, apply to all ports and all transfers within those ports. Each access request is evaluated against the memory protection table, and will fail unless there is a rule match allowing a transaction to complete successfully.

Table 73.  Result for a Sample Set of Transactions 

Operation

Source

Address Accesses

Security Access Type

Result

Comments

Read

CPU

4096

secure

Allow

Matches rule 1.

Write

CPU

536, 870, 912

secure

Allow

Matches rule 1.

Write

L3 attached masters

605, 028, 350

secure

Fail

Does not match rule 1 (out of range of the address field), does not match rule 2 (protection bit incorrect).

Read

L3 attached masters

4096

non-secure

Fail

Does not match rule 1 (AxPROT signal value wrong), does not match rule 2 (not in address range).

Write

CPU

536, 870, 912

non-secure

Allow

Matches rule 2.

Write

L3 attached masters

605, 028, 350

non-secure

Allow

Matches rule 2.

Note: If a master is using the Accelerator Coherency Port (ACP) to maintain cache coherency with the Cortex* -A9 MPCore processor, then the address ranges in the rules of the memory protection table should be made mutually exclusive, such that the secure and non-secure regions do not overlap and any area that is shared is part of the non-secure region. This configuration prevents coherency issues from occurring.

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