External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

1.13.3.5. AFI Calibration Status Signals

The PHY instantiates a sequencer which calibrates the memory interface with the memory device and some internal components such as read FIFOs and valid FIFOs. The sequencer reports the results of the calibration process to the controller through the Calibration Status Signals in the AFI interface.
Table 13.  Calibration Status Signals

Signal Name

Direction

Width

Description

afi_cal_success

Output

1

Asserted to indicate that calibration has completed successfully.

afi_cal_fail

Output

1

Asserted to indicate that calibration has failed.

afi_cal_req

Input

1

Effectively a synchronous reset for the sequencer. When this signal is asserted, the sequencer returns to the reset state; when this signal is released, a new calibration sequence begins.

afi_wlat

Output

AFI_WLAT_WIDTH

The required write latency in afi_clk cycles, between address/command and write data being issued at the PHY/controller interface. The afi_wlat value can be different for different groups; each group’s write latency can range from 0 to 63. If write latency is the same for all groups, only the lowest 6 bits are required.

afi_rlat

(1)

Output

AFI_RLAT_WIDTH

The required read latency in afi_clk cycles between address/command and read data being returned to the PHY/controller interface. Values can range from 0 to 63.

Note to Table:

  1. The afi_rlat signal is not supported for PHY-only designs. Instead, you can sample the afi_rdata_valid signal to determine when valid read data is available.

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