External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

10.4. Signal Descriptions

The following table lists the signals of the controller’s Avalon-MM slave interface.

For information on the AFI signals, refer to AFI 4.0 Specification in Functional Description - UniPHY.

Table 108.  Avalon-MM Slave Signals

Signal

Width

Direction

Avalon-MM Signal Type

Description

avl_size

1 to 11

In

burstcount

avl_ready

1

Out

waitrequest_n

avl_read_req

1

In

read

avl_write_req

1

In

write

avl_addr

 25

In

address

avl_rdata_valid

1

Out

readdatavalid

avl_rdata

18, 36, 72, 144

Out

readdata

avl_wdata

18, 36, 72, 144

In

writedata

Note: If you are using Qsys, the data width of the Avalon-MM interface is restricted to powers of two. Non-power-of-two data widths are available with the IP Catalog.
Note: The RLDRAM II controller does not support the byteenable signal. If the RLDRAM II controller is used with the Avalon-MM Efficiency Monitor and Protocol Checker, data corruption can occur if the byteenable signal on the efficiency monitor is used. For example, this can occur if using the JTAG Avalon-MM Master component to drive the efficiency monitor.

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