External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
Document Table of Contents

4.1. Features of the SDRAM Controller Subsystem

The SDRAM controller subsystem offers programming flexibility, port and bus configurability, error correction, and power management.
  • Support for double data rate 2 (DDR2), DDR3, and low-power DDR2 (LPDDR2) SDRAM
  • Flexible row and column addressing with the ability to support up to 4 Gb of memory per chip select
  • Optional 8-bit integrated error correction code (ECC) for 16- and 32-bit data widths3
  • User-configurable memory width of 8, 16, 16+ECC, 32, 32+ECC
  • User-configurable timing parameters
  • Two chip selects (DDR2 and DDR3)
  • Command reordering (look-ahead bank management)
  • Data reordering (out of order transactions)
  • User-controllable bank policy on a per port basis for either closed page or conditional open page accesses
  • User-configurable priority support with both absolute and weighted round-robin scheduling
  • Flexible FPGA fabric interface with up to 6 ports that can be combined for a data width up to 256 bits using Avalon-MM and AXI interfaces
  • Power management supporting self refresh, partial array self refresh (PASR), power down, and LPDDR2 deep power down
3 The level of ECC support is package dependent.