External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
Document Table of Contents

14.1. Generating Equivalent Design

Create a new DDR2 or DDR3 SDRAM controller with UniPHY IP core, by following the steps in the Implementing and Parameterizing Memory IP chapter of the Design Guidelines volume, and apply the following guidelines:
  • Specify the same variation name as the ALTMEMPHY variation.
  • Specify a directory different than the ALTMEMPHY design directory to prevent files from overwriting each other during generation.

To ease the migration process, ensure the UniPHY-based design you create is as similar as possible to the existing ALTMEMPHY-based design. In particular, you should ensure the following settings are the same in your UniPHY-based design:

  • PHY settings tab
  • FPGA speed grade
  • PLL reference clock
  • Memory clock frequency
  • There is no need to change the default Address and command clock phase settings; however, if you have board skew effects in your ALTMEMPHY design, enter the difference between that clock phase and the default clock phase into the Address and command clock phase settings.
  • Memory Parameters tab—all parameters must match.
  • Memory Timing tab—all parameters must match.
  • Board settings tab—all parameters must match.
  • Controller settings tab—all parameters must match
Note: In ALTMEMPHY-based designs you can turn off dynamic OCT. However, all UniPHY-based designs use dynamic parallel OCT and you cannot turn it off.