External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

1.11. PHY-to-Controller Interfaces

Various modules connect to UniPHY through specific ports.

The AFI standardizes and simplifies the interface between controller and PHY for all Intel® memory designs, thus allowing you to easily interchange your own controller code with Intel® 's high-performance controllers. The AFI PHY interface includes an administration block that configures the memory for calibration and performs necessary accesses to mode registers that configure the memory as required.

For half-rate designs, the address and command signals in the UniPHY are asserted for one mem_clk cycle (1T addressing), such that there are two input bits per address and command pin in half-rate designs. If you require a more conservative 2T addressing (where signals are asserted for two mem_clk cycles), drive both input bits (of the address and command signal) identically in half-rate designs.

The following figure shows the half-rate write operation.

Figure 13. Half-Rate Write with Word-Aligned Data


The following figure shows a full-rate write.

Figure 14. Full-Rate Write


For quarter-rate designs, the address and command signals in the UniPHY are asserted for one mem_clk cycle (1T addressing), such that there are four input bits per address and command pin in quarter-rate designs. If you require a more conservative 2T addressing (where signals are asserted for two mem_clk cycles), drive either the two lower input bits or the two upper input bits (of the address and command signal) identically.

After calibration is completed, the sequencer sends the write latency in number of clock cycles to the controller.

The AFI has the following conventions:

  • With the AFI, high and low signals are combined in one signal, so for a single chip select (afi_cs_n) interface, afi_cs_n[1:0] , location 0 appears on the memory bus on one mem_clk cycle and location 1 on the next mem_clk cycle.
    Note: This convention is maintained for all signals so for an 8 bit memory interface, the write data (afi_wdata) signal is afi_wdata[31:0], where the first data on the DQ pins is afi_wdata[7:0], then afi_wdata[15:8], then afi_wdata[23:16], then afi_wdata[31:24].
  • Spaced reads and writes have the following definitions:
    • Spaced writes—write commands separated by a gap of one controller clock (afi_clk) cycle.
    • Spaced reads—read commands separated by a gap of one controller clock (afi_clk) cycle.

The following figures show writes and reads, where the IP core writes data to and reads from the same address. In each example, afi_rdata and afi_wdata are aligned with controller clock (afi_clk) cycles. All the data in the bit vector is valid at once. These figures assume the following general points:

  • The burst length is four.
  • An 8-bit interface with one chip select.
  • The data for one controller clock (afi_clk) cycle represents data for two memory clock (mem_clk) cycles (half-rate interface).
Figure 15. Word-Aligned Writes


Notes to Figure:

  1. To show the even alignment of afi_cs_n, expand the signal (this convention applies for all other signals).
  2. The afi_dqs_burst must go high one memory clock cycle before afi_wdata_valid. Compare with the word-unaligned case.
  3. The afi_wdata_valid is asserted afi_wlat + 1 controller clock (afi_clk) cycles after chip select (afi_cs_n) is asserted. The afi_wlat indicates the required write latency in the system. The value is determined during calibration and is dependant upon the relative delays in the address and command path and the write datapath in both the PHY and the external DDR SDRAM subsystem. The controller must drive afi_cs_n and then wait afi_wlat (two in this example) afi_clks before driving afi_wdata_valid.

  4. Observe the ordering of write data (afi_wdata). Compare this to data on the mem_dq signal.
  5. In all waveforms a command record is added that combines the memory pins ras_n, cas_n and we_n into the current command that is issued. This command is registered by the memory when chip select (mem_cs_n) is low. The important commands in the presented waveforms are WR= write, ACT = activate.

Figure 16. Word-Aligned Reads


Notes to Figure:

  1. For AFI, afi_rdata_en is required to be asserted one memory clock cycle before chip select (afi_cs_n) is asserted. In the half-rate afi_clk domain, this requirement manifests as the controller driving 11 (as opposed to the 01) on afi_rdata_en.

  2. AFI requires that afi_rdata_en is driven for the duration of the read. In this example, it is driven to 11 for two half-rate afi_clks, which equates to driving to 1, for the four memory clock cycles of this four-beat burst.

  3. The afi_rdata_valid returns 15 (afi_rlat) controller clock (afi_clk) cycles after afi_rdata_en is asserted. Returned is when the afi_rdata_valid signal is observed at the output of a register within the controller. A controller can use the afi_rlat value to determine when to register to returned data, but this is unnecessary as the afi_rdata_valid is provided for the controller to use as an enable when registering read data.

  4. Observe the alignment of returned read data with respect to data on the bus.

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