External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

7.4.3.3. AXI Interface Ports

Table 93.  AXI Interface Ports

Name

Direction

Description

awid

Input

AXI write address channel ID bus.

awaddr

Input

AXI write address channel address bus.

awlen

Input

AXI write address channel length bus.

awsize

Input

AXI write address channel size bus.

awburst

Input

AXI write address channel burst bus.(Interface supports only INCR and WRAP burst types.)

awlock

Input

AXI write address channel lock bus.(Interface does not support this feature.)

awcache

Input

AXI write address channel cache bus.(Interface does not support this feature.)

awprot

Input

AXI write address channel protection bus.(Interface does not support this feature.)

awvalid

Input

AXI write address channel valid signal.

awready

Output

AXI write address channel ready signal.

wid

Input

AXI write address channel ID bus.

wdata

Input

AXI write address channel data bus.

wstrb

Input

AXI write data channel strobe bus.

wlast

Input

AXI write data channel last burst signal.

wvalid

Input

AXI write data channel valid signal.

wready

Output

AXI write data channel ready signal.

bid

Output

AXI write response channel ID bus.

bresp

Output

AXI write response channel response bus.Response encoding information:‘b00 - OKAY‘b01 - Reserved‘b10 - Reserved‘b11 - Reserved

bvalid

Output

AXI write response channel valid signal.

bready

Input

AXI write response channel ready signal.Must be set to 1. Interface does not support back pressure for write response channel.

arid

Input

AXI read address channel ID bus.

araddr

Input

AXI read address channel address bus.

arlen

Input

AXI read address channel length bus.

arsize

Input

AXI read address channel size bus.

arburst

Input

AXI read address channel burst bus.(Interface supports only INCR and WRAP burst types.)

arlock

Input

AXI read address channel lock bus.(Interface does not support this feature.)

arcache

Input

AXI read address channel cache bus.(Interface does not support this feature.)

arprot

Input

AXI read address channel protection bus.(Interface does not support this feature.)

arvalid

Input

AXI read address channel valid signal.

arready

Output

AXI read address channel ready signal.

rid

Output

AXI read data channel ID bus.

rdata

Output

AXI read data channel data bus.

rresp

Output

AXI read data channel response bus.Response encoding information:‘b00 - OKAY‘b01 - Reserved‘b10 - Data error‘b11 - Reserved

rlast

Output

AXI read data channel last burst signal.

rvalid

Output

AXI read data channel valid signal.

rready

Input

AXI read data channel ready signal.Must be set to 1. Interface does not support back pressure for write response channel.

For information about the AXI specification, refer to the ARM* website.

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