22.214.171.124. Nios® II-based Sequencer Processor
The same calibration algorithm supports all device families, with some differences. The following sections describe the calibration algorithm for DDR3 SDRAM on Stratix III devices. Calibration algorithms for other protocols and families are a subset and significant differences are pointed out when necessary. As the algorithm is fully contained in the software of the sequencer (in the C code) enabling and disabling specific steps involves turning flags on and off.
Calibration consists of the following stages:
- Initialize memory.
- Calibrate read datapath.
- Calibrate write datapath.
- Run diagnostics.
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