External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

1.9.1.1. Sharing PLLs or DLLs

To share PLLs or DLLs, follow these steps:
  1. To create a PLL or DLL master, create a UniPHY memory interface IP core. To make the PLL and/or DLL interface appear at the top-level in the core, on the PHY Settings tab in the parameter editor, set the PLL Sharing Mode and/or DLL Sharing Mode to Master.
  2. To create a PLL or DLL slave, create a second UniPHY memory interface IP core. To make the PLL and/or DLL interface appear at the top-level in the core, on the PHY Settings tab set the PLL Sharing Mode and/or DLL Sharing Mode to Slave.
  3. Connect the PLL and/or DLL sharing interfaces by following the appropriate step, below:
    • For cores generated with IP Catalog : connect the PLL and/or DLL interface ports between the master and slave cores in your wrapper RTL. When using PLL sharing, connect the afi_clk, afi_half_clk, and afi_reset_export_n outputs from the UniPHY PLL master to the afi_clk, afi_half_clk, and afi_reset_in inputs on the UniPHY PLL slave.
    • For cores generated with Qsys , connect the PLL and/or DLL interface in the Qsys GUI. When using PLL sharing, connect the afi_clk, afi_half_clk, and afi_reset_export_n outputs from the UniPHY PLL master to the afi_clk, afi_half_clk, and afi_reset_in inputs on the UniPHY PLL slave.

    Qsys supports only one-to-one conduit connections in the patch panel. To share a PLL from a UniPHY PLL master with multiple slaves, you should replicate the number of PLL sharing conduit interfaces in the Qsys patch panel by choosing Number of PLL sharing interfaces in the parameter editor.

Note: You may connect a slave UniPHY instance to the clocks from a user-defined PLL instead of from a UniPHY master. The general procedure for doing so is as follows:
  1. Make a template, by generating your IP with PLL Sharing Mode set to No Sharing, and then compiling the example project to determine the frequency and phases of the clock outputs from the PLL.
  2. Generate an external PLL using the IP Catalog flow, with the equivalent output clocks.
  3. Generate your IP with PLL Sharing Mode set to Slave, and connect the external PLL to the PLL sharing interface.

You must be very careful when connecting clock signals to the slave. Connecting to clocks with frequency or phase different than what the core expects may result in hardware failure.

Note: The signal dll_pll_locked is an internal signal from the PLL to the DLL which ensures that the DLL remains in reset mode until the PLL becomes locked. This signal is not available for use by customer logic.

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