External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

14.5. RLDRAM II Latency

The following table shows the latency in full-rate memory clock cycles.

Table 134.  RLDRAM II Latency (In Full-Rate Memory Clock Cycles) (1) (2)

Latency in Full-Rate Memory Clock Cycles

Rate

Controller Address & Command

PHY Address & Command

Memory Maximum Read

PHY Read Return

Controller Read Return

Round Trip

Round Trip Without Memory

Half

4

EWL: 1

3–8

EWL: 4

0

EWL: 12–17

EWL: 9

OWL: 2

OWL: 4

OWL: 13–18

OWL: 10

Full

2

1

3–8

4

0

10–15

7

Notes to Table:

  1. EWL = Even write latency
  2. OWL = Odd write latency

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