External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

7.5.2. Local Interface Signals

The following table lists the controller local interface signals.
Table 96.  Local Interface Signals

Signal Name

Direction

Description

avl_addr[] (1)
  

Input

Memory address at which the burst should start. By default, the IP core maps local address to the bank interleaving scheme. You can change the ordering via the Local-to-Memory Address Mapping option in the Controller Settings page.

This signal must remain stable only during the first transaction of a burst. The constantBurstBehavior property is always false for UniPHY controllers.

The IP core sizes the width of this bus according to the following equations:

  • Full rate controllers:

For one chip select: width = row bits + bank bits + column bits – 1

For multiple chip selects: width = chip bits* + row bits + bank bits + column bits – 1

If the bank address is 2 bits wide, row is 13 bits wide and column is 10 bits wide, the local address is 24 bits wide. To map local_address to bank, row and column address:

avl_addr  is 24 bits wide
avl_addr[23:11]= row address[12:0]
avl_addr[10:9] = bank address [1:0]
avl_addr[8:0] = column address[9:1]

The IP core ignores the least significant bit (LSB) of the column address (multiples of two) on the memory side, because the local data width is twice that of the memory data bus width.

  • Half rate controllers:

For one chip select: width = row bits + bank bits + column bits – 2

For multiple chip selects: width = chip bits* + row bits + bank bits + column bits – 2

If the bank address is 2 bits wide, row is 13 bits wide and column is 10 bits wide, the local address is 23 bits wide. To map local_address to bank, row and column address:

avl_addr is 23 bits wide
avl_addr[22:10] = row address[12:0]
avl_addr[9:8] = bank address [1:0]
avl_addr[7:0] = column address[9:2]

The IP core ignores two LSBs of the column address (multiples of four) on the memory side, because the local data width is four times that of the memory data bus width.

  • Quarter rate controllers:

For one chip select: width = row bits + bank bits + column bits – 3

For multiple chip selects: width = chip bits* + row bits + bank bits + column bits – 3

If the bank address is 2 bits wide, row is 13 bits wide and column is 10 bits wide, the local address is 22 bits wide.

(* chip bits is a derived value indicating the number of address bits necessary to uniquely address every memory rank in the system; this value is not user configurable.)

  • Full-rate hard memory controllers (Arria V and Cyclone V):

For one chip select: width = row bits + bank bits + column bits - log2(local avalon data width/memory DQ width)

For multiple chip selects: width = chip bits* + row bits + bank bits + column bits - log2(local avalon data width/memory data width)

If the local Avalon data width is 32, the memory DQ width is 8, the bank address is 3 bits wide, the row is 12 bits wide and the column is 8 bits wide, the local address is 21 bits wide. To map local_address to bank, row and column address:

avl_addr is 21 bits wide

avl_addr[20:9] = row address[11:0]

avl_addr[8:6] = bank address [2:0]

avl_addr[5:0] = column address[7:2]

The IP core ignores the two least significant bits of the column address on the memory side because the local data width is four times that of the memory data bus width (Multi-Port Frontend).

avl_be[]   (2)
                           
                           
                        

Input

Byte enable signal, which you use to mask off individual bytes during writes. avl_be is active high; mem_dm is active low.

To map avl_wdata and avl_be to mem_dq and mem_dm, consider a full-rate design with 32-bit avl_wdata and 16-bit mem_dq.

avl_wdata = < 22334455 >< 667788AA >< BBCCDDEE>
avl_be = < 1100 >< 0110 >< 1010  >

These values map to:

Mem_dq = <4455><2233><88AA><6677><DDEE><BBCC>
Mem_dm = <1 1 ><0 0 ><0 1 ><1 0 ><0 1 ><0 1 >
avl_burstbegin (3)
                           
                           
                        

Input

The Avalon burst begin strobe, which indicates the beginning of an Avalon burst. Unlike all other Avalon-MM signals, the burst begin signal is not dependant on avl_ready.

For write transactions, assert this signal at the beginning of each burst transfer and keep this signal high for one cycle per burst transfer, even if the slave deasserts avl_ready. The IP core samples this signal at the rising edge of phy_clk when avl_write_req is asserted. After the slave deasserts the avl_ready signal, the master keeps all the write request signals asserted until avl_ready signal becomes high again.

For read transactions, assert this signal for one clock cycle when read request is asserted and avl_addr from which the data should be read is given to the memory. After the slave deasserts avl_ready (waitrequest_n in Avalon interface), the master keeps all the read request signals asserted until avl_ready becomes high again.

avl_read_req  (4)
 

Input

Read request signal. You cannot assert read request and write request signals at the same time. The controller must deassert reset_phy_clk_n before you can assert avl_read_req.

local_refresh_req 

Input

User-controlled refresh request. If Enable User Auto-Refresh Controls option is turned on, local_refresh_req becomes available and you are responsible for issuing sufficient refresh requests to meet the memory requirements. This option allows complete control over when refreshes are issued to the memory including grouping together multiple refresh commands. Refresh requests take priority over read and write requests, unless the IP core is already processing the requests.

local_refresh_chip

Input

Controls which chip to issue the user refresh to. The IP core uses this active high signal with local_refresh_req. This signal is as wide as the memory chip select. This signal asserts a high value to each bit that represents the refresh for the corresponding memory chip.

For example: If local_refresh_chip signal is assigned with a value of 4’b0101, the controller refreshes the memory chips 0 and 2, and memory chips 1 and 3 are not refreshed.

avl_size[] (5)
                           
                                                   

Input

Controls the number of beats in the requested read or write access to memory, encoded as a binary number. In UniPHY, the IP core supports Avalon burst lengths from 1 to 1024. The IP core derives the width of this signal based on the burst count that you specify in the Maximum Avalon-MM burst length option. With the derived width, you specify a value ranging from 1 to the local maximum burst count specified.

This signal must remain stable only during the first transaction of a burst. The constantBurstBehavior property is always false for UniPHY controllers.

avl_wdata[] (6)
  

Input

Write data bus. The width of avl_wdata is twice that of the memory data bus for a full-rate controller, four times the memory data bus for a half-rate controller, and eight times the memory data bus for a quarter-rate controller. If Generate power-of-2 data bus widths for Qsys and SOPC Builder is enabled, the width is rounded down to the nearest power of 2.

avl_write_req (7)
 

Input

Write request signal. You cannot assert read request and write request signal at the same time. The controller must deassert reset_phy_clk_n before you can assert avl_write_req.

local_autopch_req (8)
                           
                           
                        

Input

User control of autoprecharge. If you turn on Enable Auto- Precharge Control, the local_autopch_req signal becomes available and you can request the controller to issue an autoprecharge write or autoprecharge read command.

These commands cause the memory to issue a precharge command to the current bank at the appropriate time without an explicit precharge command from the controller. This feature is particularly useful if you know the current read or write is the last one you intend to issue to the currently open row. The next time you need to use that bank, the access could be quicker as the controller does not need to precharge the bank before activating the row you wish to access.

Upon receipt of the local_autopch_req signal, the controller evaluates the pending commands in the command buffer and determines the most efficient autoprecharge operation to perform, reordering commands if necessary.

The controller must deassert reset_phy_clk_n before you can assert local_autopch_req.

local_self_rfsh_chip

Input

Controls which chip to issue the user refresh to. The IP core uses this active high signal with local_self_rfsh_req. This signal is as wide as the memory chip select. This signal asserts a high value to each bit that represents the refresh for the corresponding memory chip.

For example: If local_self_rfsh_chip signal is assigned with a value of 4’b0101, the controller refreshes the memory chips 0 and 2, and memory chips 1 and 3 are not refreshed.

local_self_rfsh_req

Input

User control of the self-refresh feature. If you turn on Enable Self-Refresh Controls, you can request that the controller place the memory devices into a self-refresh state by asserting this signal. The controller places the memory in the self-refresh state as soon as it can without violating the relevant timing parameters and responds by asserting local_self_rfsh_ack. You can hold the memory in the self-refresh state by keeping this signal asserted. You can release the memory from the self-refresh state at any time by deasserting local_self_rfsh_req and the controller responds by deasserting local__self_rfsh_ack when it has successfully brought the memory out of the self-refresh state.

local_init_done 

Output

When the memory initialization, training, and calibration are complete, the PHY sequencer asserts ctrl_usr_mode_rdy to the memory controller, which then asserts this signal to indicate that the memory interface is ready for use.

local_cal_success 

Output

When the memory initialization, training, and calibration completes successfully, the controller asserts this signal coincident with local_init_done to indicate the memory interface is ready for use.

local_cal_fail 

Output

When the memory initialization, training, or calibration fails, the controller asserts this signal to indicate that calibration failed. The local_init_done signal will not assert when local_cal_fail asserts.

avl_rdata[] (9)
  

 

Output

Read data bus. The width of avl_rdata is twice that of the memory data bus for a full rate controller; four times the memory data bus for a half rate controller. If Generate power-of-2 data bus widths for Qsys and SOPC Builder is enabled, the width is rounded down to the nearest power of 2.

avl_rdata_error (10)
  

Output

Asserted if the current read data has an error. This signal is only available if you turn on Enable Error Detection and Correction Logic. The controller asserts this signal with the avl_rdata_valid signal.

If the controller encounters double-bit errors, no correction is made and the controller asserts this signal.

avl_rdata_valid (11)
 
 

Output

Read data valid signal. The avl_rdata_valid signal indicates that valid data is present on the read data bus.

avl_ready (12)
                           
                           
                        

Output

The avl_ready signal indicates that the controller is ready to accept request signals. If controller asserts the avl_ready signal in the clock cycle that it asserts a read or write request, the controller accepts that request. The controller deasserts the avl_ready signal to indicate that it cannot accept any more requests. The controller can buffer eight read or write requests, after which the avl_ready signal goes low.

The avl_ready signal is deasserted when any of the following are true:

  • The Timing bank Pool is full.
  • The FIFO register that stores read data from the memory device is full.
  • The write data FIFO register is full.
  • The controller is waiting for write data when in ECC mode.
local_refresh_ack 

Output

Refresh request acknowledge, which the controller asserts for one clock cycle every time it issues a refresh. Even if you do not turn on Enable User Auto-Refresh Controls, local_refresh_ack still indicates to the local interface that the controller has just issued a refresh command.

local_self_rfsh_ack

Output

Self refresh request acknowledge signal. The controller asserts and deasserts this signal in response to the local_self_rfsh_req signal.

local_power_down_ack

Output

Auto power-down acknowledge signal. The controller asserts this signal for one clock cycle every time auto power-down is issued.

ecc_interrupt (13)
 

Output

Interrupt signal from the ECC logic. The controller asserts this signal when the ECC feature is turned on, and the controller detects an error.

Notes to Table:

  1. For the hard memory controller with multiport front end available in Arria V and Cyclone V devices, avl_addr becomes a per port value, avl_addr_#, where # is a numeral from 0–5, based on the number of ports selected in the Controller tab.
  2. For the hard memory controller with multiport front end available in Arria V and Cyclone V devices, avl_be becomes a per port value, avl_be_#, where # is a numeral from 0–5, based on the number of ports selected in the Controller tab.
  3. For the hard memory controller with multiport front end available in Arria V and Cyclone V devices, avl_burstbegin becomes a per port value, avl_burstbegin_#, where # is a numeral from 0–5, based on the number of ports selected in the Controller tab.
  4. For the hard memory controller with multiport front end available in Arria V and Cyclone V devices, avl_read_req becomes a per port value, avl_read_req_#, where # is a numeral from 0–5, based on the number of ports selected in the Controller tab.
  5. For the hard memory controller with multiport front end available in Arria V and Cyclone V devices, avl_size becomes a per port value, avl_size_#, where # is a numeral from 0–5, based on the number of ports selected in the Controller tab.
  6. For the hard memory controller with multiport front end available in Arria V and Cyclone V devices, avl_wdata becomes a per port value, avl_wdata_#, where # is a numeral from 0–5, based on the number of ports selected in the Controller tab.
  7. For the hard memory controller with multiport front end available in Arria V and Cyclone V devices, avl_write_req becomes a per port value, avl_write_req_#, where # is a numeral from 0–5, based on the number of ports selected in the Controller tab.
  8. This signal is not applicable to the hard memory controller.
  9. For the hard memory controller with multiport front end available in Arria V and Cyclone V devices, avl_rdata becomes a per port value, avl_rdata_#, where # is a numeral from 0–5, based on the number of ports selected in the Controller tab.
  10. This signal is not applicable to the hard memory controller.
  11. For the hard memory controller with multiport front end available in Arria V and Cyclone V devices, avl_rdata_valid becomes a per port value, avl_rdata_valid_#, where # is a numeral from 0–5, based on the number of ports selected in the Controller tab.
  12. For the hard memory controller with multiport front end available in Arria V and Cyclone V devices, avl_ready becomes a per port value, avl_ready_#, where # is a numeral from 0–5, based on the number of ports selected in the Controller tab.
  13. This signal is not applicable to the hard memory controller.

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