External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
Document Table of Contents

5.2. HPC II Memory Controller Architecture

The memory controller logic block uses an Avalon® Streaming ( Avalon® -ST) interface as its native interface, and communicates with the PHY layer by the Altera PHY Interface (AFI).

The following figure shows a block diagram of the memory controller architecture.

Figure 52. Memory Controller Architecture Block Diagram

Avalon® -ST Input Interface

The Avalon® -ST interface serves as the entry point to the memory controller, and provides communication with the requesting data masters.

For information about the Avalon® interface, refer to Avalon® Interface Specifications.

AXI to Avalon® -ST Converter

The HPC II memory controller includes an AXI to Avalon® -ST converter for communication with the AXI protocol. The AXI to Avalon® -ST converter provides write address, write data, write response, read address, and read data channels on the AXI interface side, and command, write data, and read data channels on the Avalon® -ST interface side.


The AXI protocol employs a handshaking process similar to the Avalon® -ST protocol, based on ready and valid signals.

Command Channel Implementation

The AXI interface includes separate read and write channels, while the Avalon® -ST interface has only one command channel. Arbitration of the read and write channels is based on these policies:

  • Round robin
  • Write priority—write channel has priority over read channel
  • Read priority—read channel has priority over write channel

You can choose an arbitration policy by setting the COMMAND_ARB_TYPE parameter to one of ROUND_ROBIN, WRITE_PRIORITY, or READ_PRIORITY in the alt_mem_ddrx_axi_st_converter.v file.

Data Ordering

The AXI specification requires that write data IDs must arrive in the same order as write address IDs are received. Similarly, read data must be returned in the same order as its associated read address is received.

Consequently, the AXI to Avalon® -ST converter does not support interleaving of write data; all data must arrive in the same order as its associated write address IDs. On the read side, the controller returns read data based on the read addresses received.

Burst Types

The AXI to Avalon® -ST converter supports the following burst types:

  • Incrementing burst—the address for each transfer is an increment of the previous transfer address; the increment value depends on the size of the transfer.
  • Wrapping burst—similar to the incrementing burst, but wraps to the lower address when the burst boundary is reached. The starting address must be aligned to the size of the transfer. Burst length must be 2, 4, 8, or 16. The burst wrap boundary = burst size * burst length.