External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
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8.3. RLDRAM 3 AFI Protocol

The RLDRAM 3 UniPHY-based IP communicates with the memory controller using an AFI interface that follows the AFI 3.0 specification. To maximize bus utilization efficiency, the RLDRAM 3 UniPHY-based IP can issue multiple memory read/write operations within a single AFI cycle.

The following figure illustrates AFI bus activity when a quarter-rate controller issues four consecutive burst-length 2 read requests.

Figure 60. AFI Bus Activity for Quarter-Rate Controller Issuing Four Burst-Length 2 Read Requests

The controller does not have to begin a read or write command using channel 0 of the AFI bus. The flexibility afforded by being able to begin a command on any bus channel can facilitate command scheduling in the memory controller.

The following figure illustrates the AFI bus activity when a quarter-rate controller issues a single burst-length 4 read command to the memory on channel 1 of the AFI bus.

Figure 61. AFI Bus Activity for Quarter-Rate Controller Issuing One Burst-Length 4 Read Request
Note: For information on the AFI, refer to AFI 3.0 Specification in Functional Description - UniPHY.