11.3. RLDRAM 3 AFI Protocol
The following figure illustrates AFI bus activity when a quarter-rate controller issues four consecutive burst-length 2 read requests.
The controller does not have to begin a read or write command using channel 0 of the AFI bus. The flexibility afforded by being able to begin a command on any bus channel can facilitate command scheduling in the memory controller.
The following figure illustrates the AFI bus activity when a quarter-rate controller issues a single burst-length 4 read command to the memory on channel 1 of the AFI bus.
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