External Memory Interface Handbook Volume 3: Reference Material

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ID 683841
Date 7/24/2019
Public
Document Table of Contents

16.15. Document Revision History

Date Version Changes
May 2017 2017.05.08
  • Added Using the EMIF Debug Toolkit with Arria 10 HPS Interfaces topic.
  • Added Calibration Adjustment Delay Step Sizes for Arria 10 Devices topic.
  • Replaced EMIF Configurable Traffic Generator 2.0 section with new Traffic Generator 2.0 section.
  • Rebranded as Intel.
October 2016 2016.10.31 Maintenance release.
May 2016 2016.05.02
  • Added additional option to step 1 of Establishing Communication to Connections.
  • Added sentence to second bullet in Eye Diagram.
  • Expanded step 4 and added step 5, in Determining Margin.
  • Added Configuring the Traffic Generator 2.0 and The Traffic Generator 2.0 Report.
November 2015 2015.11.02
  • Changed title of Architecture section to User Interface.
  • Added sentence to Driver Margining section stating that driver margining is not available if ECC is enabled.
  • Removed note that the memory map for Arria 10 On-Chip Debug would be available in a future release.
  • Created separate On-Chip Debug sections for UniPHY-based EMIF IP and Arria 10 EMIF IP.
  • Changed title of Driver Margining (Arria 10 only) section to Driver Margining for Arria 10 EMIF IP.
  • Changed title of Read Setting and Apply Setting Commands (Arria 10 only) to Read Setting and Apply Setting Commands for Arria 10 EMIF IP.
  • Added section Example Tcl Script for Running the EMIF Debug Toolkit.
  • Changed instances of Quartus II to Quartus Prime.
May 2015 2015.05.04
  • Added Determining the Failing Calibration Stage for a Cyclone V or Arria V HPS SDRAM Controller.
  • Changed occurrences of On-Chip Debug Toolkit to On-Chip Debug Port.
  • Added Driver Margining (Arria 10 only) and Determining Margin.
  • Added Read Setting and Apply Setting Commands (Arria 10 only) and Reading or Applying Calibration Settings.
December 2014 2014.12.15
  • Added paragraph to step 5 of Generating IP With the Debug Port.
  • Added mention of seq_debug_clk and seq_debug_reset_in to step 5 of Generating IP With the Debug Port.
August 2014 2014.08.15 Maintenance release.
December 2013 2013.12.16 Maintenance release.
November 2012 2.2
  • Changes to Setup and Use and General Workflow sections.

  • Added EMIF On-Chip Debug Toolkit section
  • Changed chapter number from 11 to 13.
August 2012 2.1 Added table of debugging tips.
June 2012 2.0
  • Revised content for new UnIPHY EMIF Toolkit.
  • Added Feedback icon.
November 2011 1.0 Harvested 11.0 DDR2 and DDR3 SDRAM Controller with UniPHY EMIF Toolkit content.

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