External Memory Interface Handbook Volume 3: Reference Material

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ID 683841
Date 7/24/2019
Public
Document Table of Contents

17.7. Simulating your Design

You must use the UniPHY memory model to simulate your new design.

To use the UniPHY memory model, follow these steps:

  1. Edit your instantiation of the UniPHY datapath to ensure the local_init_done, local_cal_success, local_cal_fail, soft_reset_n, oct_rdn, oct_rup, reset_phy_clk_n, and phy_clk signals are at the top-level entity so that an instantiating testbench can refer to those signals.
  2. To use the UniPHY testbench and memory model, generate the example design when generating your IP instantiation.
  3. Specify that your third-party simulator should use the UniPHY testbench and memory model instead of the ALTMEMPHY memory model, as follows:
    1. On the Assignments menu, point to Settings and click the Project Settings window.
    2. Select the Simulation tab, click Test Benches, click Edit, and replace the ALTMEMPHY testbench files with the following files:
      • \<project directory>\<variation name>_example_design\simulation\verilog\submodules\altera_avalon_clock_source.sv or \<project directory>\<variation name>_example_design\simulation\vhdl\submodules\altera_avalon_clock_source.vhd
      • \<project directory>\<variation name>_example_design\simulation\verilog\submodules\altera_avalon_reset_source.sv or \<project directory>\<variation name>_example_design\simulation\vhdl\submodules\altera_avalon_reset_source.vhd
      • \<project directory>\<variation name>_example_design\simulation\verilog\<variation name>_example_sim.v or \uniphy\<variation name>_example_design\simulation\vhdl\<variation name>_example_sim.vhd
      • \<project directory>\<variation name>_example_design\simulation\verilog\submodules\verbosity_pkg.sv
      • \<project directory>\<variation name>_example_design\simulation\verilog\submodules\status_checker_no_ifdef_params.sv or \<project directory>\<variation name>_example_design\simulation\vhdl\submodules\status_checker_no_ifdef_params.sv
      • \<project directory>\<variation name>_example_design\simulation\verilog\submodules\alt_mem_if_common_ddr_mem_model_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en.sv or \<project directory>\<variation name>_example_design\simulation\vhdl\submodules\alt_mem_if_common_ddr_mem_model_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en.sv
      • \<project directory>\<variation name>_example_design\simulation\verilog\submodules\alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en or \<project directory>\<variation name>_example_design\simulation\vhdl\submodules\alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en
  4. Open the <variation name>_example_sim.v file and find the UniPHY-generated simulation example design module name below: <variation name>_example_sim_e0.
  5. Change the module name above to the name of your top-level design module.
  6. Refer to the following table and update the listed port names of the example design in the UniPHY-generated <variation name>_example_sim.v file.
Table 139.  Example Design Port Names

Example Design Name

New Name

pll_ref_clk

Rename to clock_source.

mem_a

Rename to mem_addr.

mem_ck

Rename to mem_clk.

mem_ck_n

Rename to mem_clk_n.

mem_dqs_n

Rename to mem_dqsn.

drv_status_pass

Rename to pnf.

afi_clk

Rename to phy_clk.

afi_reset_n

Rename to reset_phy_clk_n.

drv_status_fail

This signal is not available, so comment out this output.

afi_half_clk

This signal is not exposed to the top-level design, so comment out this output.

For more information about generating example simulation files, refer to Simulating Memory IP, in volume 2 of the External Memory Interface Handbook.

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