External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

6.3. SDRAM Controller Memory Options

Bank selects, and row and column address lines can be configured to work with SDRAMs of various technology and density combinations.

Table 64.  SDRAM Controller Interface Memory Options

Memory Type

4

Mbits

Column Address Bit Width

Bank Select Bit Width

Row Address Bit Width

Page Size

MBytes

DDR2

256

10

2

13

1024

32

512

10

2

14

1024

64

1024 (1 Gb)

10

3

14

1024

128

2048 (2 Gb)

10

3

15

1024

256

4096 (4 Gb)

10

3

16

1024

512

DDR3

512

10

3

13

1024

64

1024 (1 Gb)

10

3

14

1024

128

2048 (2 Gb)

10

3

15

1024

256

4096 (4 Gb)

10

3

16

1024

512

LPDDR2

64

9

2

12

512

8

128

10

2

12

1024

16

256

10

2

13

1024

32

512

11

2

13

2048

64

1024 (1 Gb) -S2 5

11

2

14

2048

128

1024 (1 Gb) -S4 6

11

3

13

2048

128

2048

(2 Gb) - S2 5

11

2

15

2048

256

2048

(2 Gb) -S4 6

11

3

14

2048

256

4096

(4 Gb)

12

3

14

4096

512

4 For all memory types shown in this table, the DQ width is 8.
5 S2 signifies a 2n prefetch size
6 S4 signifies a 4n prefetch size

Did you find the information on this page useful?

Characters remaining:

Feedback Message