External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

7.5.3. Controller Interface Signals

The following table lists the controller interface signals.
Table 97.  Interface Signals        

Signal Name

Direction

Description

mem_dq[]

Bidirectional

Memory data bus. This bus is half the width of the local read and write data busses.

mem_dqs[]

Bidirectional

Memory data strobe signal, which writes data into the memory device and captures read data into the Intel device.

mem_dqs_n[]

Bidirectional

Inverted memory data strobe signal, which with the mem_dqs signal improves signal integrity.

mem_ck 

Output

Clock for the memory device.

mem_ck_n 

Output

Inverted clock for the memory device.

mem_addr[]

Output

Memory address bus.

mem_ac_parity  (1)

Output

Address or command parity signal generated by the PHY and sent to the DIMM. DDR3 SDRAM only.

mem_ba[]

Output

Memory bank address bus.

mem_cas_n

Output

Memory column address strobe signal.

mem_cke[]

Output

Memory clock enable signals.

mem_cs_n[]

Output

Memory chip select signals.

mem_dm[]

Output

Memory data mask signal, which masks individual bytes during writes.

mem_odt

Output

Memory on-die termination control signal.

mem_ras_n

Output

Memory row address strobe signal.

mem_we_n

Output

Memory write enable signal.

parity_error_n  (1)

Output

This signal is not used and should be ignored. The PHY does not have capture circuity to trigger on the falling edge of mem_error_out_n. See below for a complete description of mem_error_out_n, and recommendations.

mem_err_out_n  (1)

Input

This is an output of registered DIMMs. When an address-and-command parity error is detected, DDR3 registered DIMMs assert the mem_err_out_n signal in accordance with the memory buffer configuration. Unlike ECC on the data bus, the controller does not automatically correct errors on the address-and-command bus. You should connect this pin to your own falling edge detection circuitry in order to capture when a parity error occurs. Upon error detection, action may be taken such as causing a system interrupt, or an appropriate event.

Note:

  1. This signal is for registered DIMMs only.

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