12.3.1. Synthesis Example Design
- A traffic generator, which is a synthesizable Avalon-MM example driver that implements a pseudo-random pattern of reads and writes to a parameterized number of addresses. The traffic generator also monitors the data read from the memory to ensure it matches the written data and asserts a failure otherwise.
- An instance of the UniPHY memory interface, which includes a memory controller that moderates between the Avalon-MM interface and the AFI interface, and the UniPHY, which serves as an interface between the memory controller and external memory devices to perform read and write operations.
If you are using the Ping Pong PHY feature, the synthesis example design includes two traffic generators issuing commands to two independent memory devices through two independent controllers and a common PHY, as shown in the following figure.
If you are using RLDRAM 3, the traffic generator in the synthesis example design communicates directly with the PHY using AFI, as shown in the following figure.
You can obtain the synthesis example design by generating your IP core. The files related to the synthesis example design reside at < variation_name >_ example_design / example_project. The synthesis example design includes a Quartus Prime project file (< variation_name >_ example_design / example_project /< variation_name >_example.qpf). The Quartus Prime project file can be compiled in the Quartus Prime software, and can be run on hardware.
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