External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

5.5.4. MPFE Setup Guidelines

The following instructions provide information on configuring the multi-port front end of the hard memory interface.
  1. To enable the hard memory interface, turn on Enable Hard External Memory Interface in the Interface Type tab in the parameter editor.
  2. To export bonding interface ports to the top level, turn on Export bonding interface in the Multiple Port Front End pulldown on the Controller Settings tab in the parameter editor.
    Note: The system exports three bonding-in ports and three bonding-out ports. You must generate two controllers and connect the bonding ports manually.
  3. To expand the interface data width from a maximum of 32 bits to a maximum of 40 bits, turn on Enable Avalon-MM data for ECC in the Multiple Port Front End pulldown on the Controller Settings tab in the parameter editor.
    Note: The controller does not perform ECC checking when this option is turned on.
  4. Select the required Number of ports for the multi-port front end in the Multiple Port Front End pulldown on the Controller Settings tab in the parameter editor.
    Note: The maximum number of ports is 6, depending on the port type and width. The maximum port width is 256 bits, which is the maximum data width of the read data FIFO and write data FIFO buffers.
  5. The table in the Multiple Port Front End pulldown on the Controller Settings tab in the parameter editor lists the ports that are created. The columns in the table describe each port, as follows:
    • Port: Indicates the port number.
    • Type: Indicates whether the port is read only, write only, or bidirectional.
    • Width: To achieve optimum MPFE throughput, Intel recommends setting the MPFE data port width according to the following calculation:

      2 x (frequency ratio of HMC to user logic) x (interface data width)

      For example, if the frequency of your user logic is one-half the frequency of the hard memory controller, you should set the port width to be 4x the interface data width. If the frequency ratio of the hard memory controller to user logic is a fractional value, you should use a larger value; for example, if the ratio is 1.5, you can use 2.

    • Priority: The priority setting specifies the priority of the slave port, with higher values representing higher priority. The slave port with highest priority is served first.
    • Weight: The weight setting has a range of values of 0–31, and specifies the relative priority of a slave port, with higher weight representing higher priority. The weight value can determine relative bandwidth allocations for slave ports with the same priority values.For example, if two ports have the same priority value, and weight values of 4 and 6, respectively, the port with a weight of 4 will receive 40% of the bus bandwidth, while the port with a weight of 6 will receive 60% of the bus bandwidth—assuming 100% total available bus bandwidth.

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