External Memory Interface Handbook Volume 3: Reference Material

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ID 683841
Date 7/24/2019
Public
Document Table of Contents

15.2. DDR3 Timing Diagrams

This topic contains timing diagrams for UniPHY-based external memory interface IP for DDR3 protocols.

The following figures present timing diagrams based on a Stratix III device

Figure 187. Half-Rate DDR3 SDRAM Read


Notes for the above Figure:

  1. Controller receives read command.
  2. Controller issues activate command to PHY.
  3. PHY issues activate command to memory.
  4. Controller issues read command to PHY.
  5. PHY issues read command to memory.
  6. PHY receives read data from memory.
  7. Controller receives read data from PHY.
  8. User logic receives read data from controller.
Figure 188. Half-Rate DDR3 SDRAM Writes


Notes for the above Figure:

  1. Controller receives write command.
  2. Controller receives write data.
  3. Controller issues activate command to PHY.
  4. PHY issues activate command to memory.
  5. Controller issues write command to PHY.
  6. PHY issues write command to memory.
  7. Controller sends write data to PHY.
  8. PHY sends write data to memory.
Figure 189. Quarter-Rate DDR3 SDRAM Reads


Notes for the above Figure:

  1. Controller receives read command.
  2. Controller issues activate command to PHY.
  3. PHY issues activate command to memory.
  4. Controller issues read command to PHY.
  5. PHY issues read command to memory.
  6. PHY receives read data from memory
  7. Controller receives read data from PHY
  8. User logic receives read data from controller.
Figure 190. Quarter-Rate DDR3 SDRAM Writes


Notes for the above Figure:

  1. Controller receives write command.
  2. Controller receives write data.
  3. Controller issues activate command to PHY
  4. PHY issues activate command to memory.
  5. Controller issues write command to PHY
  6. PHY issues write command to memory
  7. Controller sends write data to PHY
  8. PHY sends write data to memory.

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