External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
Document Table of Contents

4. Functional Description—HPS Memory Controller

The hard processor system (HPS) SDRAM controller subsystem provides efficient access to external SDRAM for the Arm* Cortex* -A9 microprocessor unit (MPU) subsystem, the level 3 (L3) interconnect, and the FPGA fabric.
Note: This chapter applies to the HPS architecture of Arria V and Cyclone V memory controllers only.

The SDRAM controller provides an interface between the FPGA fabric and HPS. The interface accepts Advanced Microcontroller Bus Architecture ( AMBA* ) Advanced eXtensible Interface ( AXI* ) and Avalon® Memory-Mapped (Avalon-MM) transactions, converts those commands to the correct commands for the SDRAM, and manages the details of the SDRAM access.