Visible to Intel only — GUID: sfo1411577352386
Ixiasoft
Visible to Intel only — GUID: sfo1411577352386
Ixiasoft
6.9. Clocks
Clock Name |
Description |
---|---|
|
Clock for PHY |
|
Clock for MPFE, single-port controller, CSR access, and PHY |
|
Clock for PHY that provides up to 2 times ddr_dq_clk frequency |
|
Clock for CSR interface |
|
Clock for MPU interface |
|
Clock for L3 interface |
|
Six separate clocks used for the FPGA-to-HPS SDRAM ports to the FPGA fabric |
In terms of clock relationships, the FPGA fabric connects the appropriate clocks to write data, read data, and command ports for the constructed ports.
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