External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

6.9. Clocks

All clocks are assumed to be asynchronous with respect to the ddr_dqs_clk memory clock. All transactions are synchronized to memory clock domain.
Table 74.  SDRAM Controller Subsystem Clock Domains 

Clock Name

Description

ddr_dq_clk

Clock for PHY

ddr_dqs_clk

Clock for MPFE, single-port controller, CSR access, and PHY

ddr_2x_dqs_clk

Clock for PHY that provides up to 2 times ddr_dq_clk frequency

l4_sp_clk

Clock for CSR interface

mpu_l2_ram_clk

Clock for MPU interface

l3_main_clk

Clock for L3 interface

f2h_sdram_clk[5:0]

Six separate clocks used for the FPGA-to-HPS SDRAM ports to the FPGA fabric

In terms of clock relationships, the FPGA fabric connects the appropriate clocks to write data, read data, and command ports for the constructed ports.

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